From 8784c80125423fcd08d123d9d1b93ee8db3f2c3c Mon Sep 17 00:00:00 2001 From: ggn Date: Thu, 24 Mar 2022 12:29:46 +0200 Subject: [PATCH 1/4] Get rid of some old and deprecated macros --- dsp56k_amode.c | 88 ++++++++++++++++----------------- dsp56k_amode.h | 18 +++---- mach.c | 132 ++++++++++++++++++++++++------------------------- rmac.h | 23 --------- 4 files changed, 119 insertions(+), 142 deletions(-) diff --git a/dsp56k_amode.c b/dsp56k_amode.c index 4b80f8c..22ed0e1 100644 --- a/dsp56k_amode.c +++ b/dsp56k_amode.c @@ -1062,7 +1062,7 @@ static inline LONG check_x_y(LONG ea1, LONG S1) if (K_D1 == K_D2) return error("unrecognised X:Y: parallel move syntax: D1 and D2 cannot be the same in 'X:ea,D1 Y:eay,D2'"); - inst = B16(11000000, 00000000) | w; + inst = 0b1100000000000000 | w; inst |= ea1 | D1 | ea2 | D2; return inst; } @@ -1148,7 +1148,7 @@ static inline LONG check_x_y(LONG ea1, LONG S1) ea2 |= eay_temp; //OR eay back from temp - inst = B16(10000000, 00000000) | w; + inst = 0b1000000000000000 | w; inst |= (ea1 & 0x1f) | D1 | S2 | ea2; return inst; } @@ -1210,10 +1210,10 @@ x_checkea_right: if (ea1 == -1) return error("unrecognised X:R parallel move syntax: absolute address not allowed in 'a,X:ea x0,a'"); - if (ea1 == B8(00110100)) + if (ea1 == 0b00110100) return error("unrecognised X:R parallel move syntax: immediate data not allowed in 'a,X:ea x0,a'"); - inst = B16(00001000, 00000000) | ea1 | (0 << 8); + inst = 0b0000100000000000 | ea1 | (0 << 8); return inst; } else if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_B) @@ -1228,10 +1228,10 @@ x_checkea_right: if (ea1 == -1) return error("unrecognised X:R parallel move syntax: absolute address not allowed in 'b,X:ea x0,b'"); - if (ea1 == B8(00110100)) + if (ea1 == 0b00110100) return error("unrecognised X:R parallel move syntax: immediate data not allowed in 'b,X:ea x0,b'"); - inst = B16(00001001, 00000000) | ea1 | (1 << 8); + inst = 0b0000100100000000 | ea1 | (1 << 8); return inst; } else if (*tok == KW_A || *tok == KW_B) @@ -1276,7 +1276,7 @@ x_checkea_right: if (*tok != EOL) return error("unrecognised X:R parallel move syntax: unexpected text after 'X:eax,D1 S2,S2'"); - inst = B16(00010000, 00000000) | (0 << 7); + inst = 0b0001000000000000 | (0 << 7); inst |= ea1 | D1 | S2 | D2; return inst; } @@ -1363,7 +1363,7 @@ x_check_immed: if (*tok == EOL) { // 'X:ea,D' - inst = inst | B8(01000000) | (1 << 7); + inst = inst | 0b01000000 | (1 << 7); inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8); inst |= ea1; @@ -1389,7 +1389,7 @@ x_check_immed: if (*tok != EOL) return error("unrecognised X:R parallel move syntax: expected EOL after X:ea,D1 S2,D2"); - inst = B16(00010000, 00000000) | (1 << 7); + inst = 0b0001000000000000 | (1 << 7); inst |= ((D1 & 0x8) << (12 - 4)) + ((D1 & 1) << 10); inst |= (S2 & 1) << 9; inst |= (D2 & 1) << 8; @@ -1411,7 +1411,7 @@ x_check_immed: if (*tok == EOL) { // 'S,X:ea' - inst = inst | B8(01000000) | (0 << 7); + inst = inst | 0b01000000 | (0 << 7); inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8); inst |= ea1; @@ -1485,7 +1485,7 @@ x_gotea1: //'X:ea,D' D1 = SDreg(*tok++); - inst = inst | B8(01000000) | (1 << 7); + inst = inst | 0b01000000 | (1 << 7); inst |= ea1; inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8); return inst; @@ -1496,7 +1496,7 @@ x_gotea1: if (*tok == EOL) { //'S,X:ea' - inst = inst | B8(01000000) | (0 << 7); + inst = inst | 0b01000000 | (0 << 7); inst |= ea1; inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8); return inst; @@ -1542,7 +1542,7 @@ x_gotea1: if (*tok != EOL) return error("unrecognised X:R parallel move syntax: unexpected text after 'X:eax,D1 S2,S2'"); - inst = B16(00010000, 00000000) | (W << 7); + inst = 0b0001000000000000 | (W << 7); inst |= ea1 | D1 | S2 | D2; return inst; } @@ -1691,7 +1691,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) if (*tok == EOL && S1 != 0) { // 'S,Y:aa' - inst = B16(01001000, 00000000); + inst = 0b0100100000000000; inst |= dspImmedEXVAL; inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8); return inst; @@ -1712,7 +1712,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) if (*tok == EOL && S1 != 0) { // 'S,Y:ea' - inst = B16(01001000, 01110000); + inst = 0b0100100001110000; inst |= ea1; inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8); if (ea1 == DSP_EA_ABS) @@ -1733,7 +1733,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) if (*tok != EOL) return error("unrecognised Y: parallel move syntax: expected EOL after 'Y:ea,D'"); - inst |= B16(00000000, 01110000); + inst |= 0b0000000001110000; inst |= ea1; inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8); if (ea1 == DSP_EA_ABS) @@ -1811,7 +1811,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) if (S1 != 0 && *tok == EOL) { // 'S,Y:ea' - inst = B16(01001000, 01000000); + inst = 0b0100100001000000; inst |= ea1; inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8); return inst; @@ -1845,7 +1845,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) default: return error("unrecognised R:Y parallel move syntax: D2 can only be y0, y1, a or b after 'S1,D1 Y:ea'"); } - inst = B16(00010000, 11000000); + inst = 0b0001000011000000; inst |= S1 | D1 | D2; inst |= ea1; return inst; @@ -1861,7 +1861,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) { //'Y:ea,D' D1 = SDreg(*tok++); - inst |= B16(00000000, 01000000); + inst |= 0b0000000001000000; inst |= ea1; inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8); return inst; @@ -2027,7 +2027,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) else S1 &= 7; - inst = B16(01000000, 00000000); + inst = 0b0100000000000000; inst |= dspImmedEXVAL; inst |= ((S1 & 0x4) << (11 - 2)) + ((S1 & 3) << 8); return inst; @@ -2045,7 +2045,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) if (ea1 == DSP_EA_ABS) deposit_extra_ea = DEPOSIT_EXTRA_WORD; - inst |= B16(01000000, 01110000); + inst |= 0b0100000001110000; inst |= ((S1 & 0x4) << (11 - 2)) + ((S1 & 3) << 8); inst |= ea1; return inst; @@ -2076,7 +2076,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) if (*tok != EOL) return error("unrecognised L: parallel move syntax: expected End-Of-Line after L:aa,D"); - inst &= B16(11111111, 10111111); + inst &= 0b1111111110111111; inst |= dspImmedEXVAL; inst |= ((immreg & 0x4) << (11 - 2)) + ((immreg & 3) << 8); return inst; @@ -2103,7 +2103,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) if (*tok != EOL) return error("unrecognised L: parallel move syntax: expected End-Of-Line after L:ea,D"); - inst |= B16(00000000, 00110000); + inst |= 0b0000000000110000; inst |= ((D1 & 0x4) << (11 - 2)) + ((D1 & 3) << 8); return inst; } @@ -2143,7 +2143,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) if (*tok == EOL) { // 'S,L:ea' - inst = B16(01000000, 01000000); + inst = 0b0100000001000000; if (S1 == KW_A) S1 = 4; @@ -2510,7 +2510,7 @@ LONG parmoves(WORD dest) if (*tok == EOL) { // No parallel move - return B16(00100000, 00000000); + return 0b0010000000000000; } if (*tok == '#') @@ -2572,7 +2572,7 @@ LONG parmoves(WORD dest) { // '#xx,D' // value fits in 8 bits - immediate move - inst = B16(00100000, 00000000) + (immreg << 8) + (uint32_t)dspImmedEXVAL; + inst = 0b0010000000000000 + (immreg << 8) + (uint32_t)dspImmedEXVAL; return inst; } else @@ -2597,7 +2597,7 @@ LONG parmoves(WORD dest) // X or Y Data move. I don't think it matters much // which of the two it will be, so let's use X. deposit_immediate_long_with_register: - inst = B16(01000000, 11110100); + inst = 0b0100000011110100; inst |= ((immreg & 0x18) << (12 - 3)) + ((immreg & 7) << 8); deposit_extra_ea = DEPOSIT_EXTRA_WORD; return inst; @@ -2607,7 +2607,7 @@ deposit_immediate_long_with_register: { // value fits in 8 bits - immediate move deposit_immediate_short_with_register: - inst = B16(00100000, 00000000) + (immreg << 8) + (uint32_t)dspImmedEXVAL; + inst = 0b0010000000000000 + (immreg << 8) + (uint32_t)dspImmedEXVAL; return inst; } else @@ -2632,7 +2632,7 @@ deposit_immediate_short_with_register: // '#xx,D' - I mode // No visibility of the number so let's add a fixup for this AddFixup(FU_DSPIMM8, sloc, dspImmedEXPR); - inst = B16(00100000, 00000000); + inst = 0b0010000000000000; inst |= ((immreg & 0x18) << (11 - 3)) + ((immreg & 7) << 8); return inst; } @@ -2703,7 +2703,7 @@ deposit_immediate_short_with_register: { // Just deposit a float fixup AddFixup(FU_DSPIMMFL8, sloc, dspImmedEXPR); - inst = B16(00100000, 00000000); + inst = 0b0010000000000000; inst |= ((immreg & 0x18) << (12 - 3)) + ((immreg & 7) << 8); return inst; } @@ -2742,7 +2742,7 @@ deposit_immediate_short_with_register: if (*tok != EOL) return error("unrecognised X:R parallel move syntax: expected end-of-line after '#xxxxxx,D1 S2,D2'"); - inst = B16(00010000, 10110100) | D1 | S2 | D2; + inst = 0b0001000010110100 | D1 | S2 | D2; deposit_extra_ea = DEPOSIT_EXTRA_WORD; return inst; } @@ -2759,7 +2759,7 @@ deposit_immediate_short_with_register: return error("expected ':' after 'X' in parallel move (i.e. X:)"); // 'X:ea,D' or 'X:aa,D' or 'X:ea,D1 S2,D2' or 'X:eax,D1 Y:eay,D2' or 'X:eax,D1 S2,Y:eay' - return parse_x(1, B16(01000000, 00000000), 0, 1); + return parse_x(1, 0b0100000000000000, 0, 1); } else if (*tok == KW_Y) { @@ -2773,7 +2773,7 @@ deposit_immediate_short_with_register: return error("expected ':' after 'Y' in parallel move (i.e. Y:)"); // 'Y:ea,D' or 'Y:aa,D' - return parse_y(B16(01001000, 10000000), 0, 0, 0); + return parse_y(0b0100100010000000, 0, 0, 0); } else if (*tok == KW_L) { @@ -2782,7 +2782,7 @@ deposit_immediate_short_with_register: if (*tok++ != ':') return error("expected ':' after 'L' in parallel move (i.e. L:)"); - return parse_l(1, B16(01000000, 11000000), 0); + return parse_l(1, 0b0100000011000000, 0); } else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2) || (*tok >= KW_A10 && *tok <= KW_BA)) { @@ -2810,7 +2810,7 @@ parse_everything_else: if (*tok++ != ':') return error("unrecognised X: parallel move syntax: expected ':' after 'S,X'"); - return parse_x(0, B16(01000000, 00000000), S1, 1); + return parse_x(0, 0b0100000000000000, S1, 1); } else if (*tok == KW_Y) { @@ -2820,7 +2820,7 @@ parse_everything_else: if (*tok++ != ':') return error("unrecognised Y: parallel move syntax: expected ':' after 'S,Y'"); - return parse_y(B16(0000000, 00000000), S1, 0, 0); + return parse_y(0b000000000000000, S1, 0, 0); } else if (*tok == KW_L) { @@ -2830,7 +2830,7 @@ parse_everything_else: if (*tok++ != ':') return error("unrecognised L: parallel move syntax: expected ':' after 'S,L'"); - return parse_l(1, B16(00000000, 00000000), L_S1); + return parse_l(1, 0b0000000000000000, L_S1); } else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) { @@ -2842,7 +2842,7 @@ parse_everything_else: if (*tok == EOL) { // R 'S,D' - inst = B16(00100000, 00000000); + inst = 0b0010000000000000; inst |= (S1 << 5) | (D1); return inst; } @@ -2852,7 +2852,7 @@ parse_everything_else: tok++; if (*tok++ != ':') return error("expected ':' after 'Y' in parallel move (i.e. Y:)"); - return parse_y(B16(00010000, 01000000), S1, D1, 0); + return parse_y(0b0001000001000000, S1, D1, 0); } else if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1) @@ -2877,7 +2877,7 @@ parse_everything_else: if (ea1 == ERROR) return ERROR; - inst = B16(00001000, 10000000); + inst = 0b0000100010000000; inst |= 0 << 8; inst |= ea1; return inst; @@ -2899,7 +2899,7 @@ parse_everything_else: if (ea1 == ERROR) return ERROR; - inst = B16(00001000, 10000000); + inst = 0b0000100010000000; inst |= 1 << 8; inst |= ea1; return inst; @@ -2921,7 +2921,7 @@ parse_everything_else: if (ea1 == ERROR) return ERROR; - inst = B16(00010000, 01000000); + inst = 0b0001000001000000; inst |= (S1 & 1) << 11; inst |= (D1 & 1) << 10; inst |= ((S2 & 8) << (10 - 4)) | ((S2 & 1) << 8); @@ -2970,7 +2970,7 @@ parse_everything_else: { if (D1 == 4 || D1 == 5) { - inst = B16(00010000, 11110100); + inst = 0b0001000011110100; inst |= (S1 & 1) << 11; inst |= (D1 & 1) << 10; inst |= D2; @@ -3049,7 +3049,7 @@ parse_everything_else: } } - inst = B16(00100000, 01000000); + inst = 0b0010000001000000; inst |= ea1; return inst; } diff --git a/dsp56k_amode.h b/dsp56k_amode.h index a462ccd..5f2d53f 100644 --- a/dsp56k_amode.h +++ b/dsp56k_amode.h @@ -73,15 +73,15 @@ // DSP EA modes -#define DSP_EA_POSTDEC B8(00000000) -#define DSP_EA_POSTINC B8(00001000) -#define DSP_EA_POSTDEC1 B8(00010000) -#define DSP_EA_POSTINC1 B8(00011000) -#define DSP_EA_NOUPD B8(00100000) -#define DSP_EA_INDEX B8(00101000) -#define DSP_EA_PREDEC1 B8(00111000) -#define DSP_EA_ABS B8(00110000) -#define DSP_EA_IMM B8(00110100) +#define DSP_EA_POSTDEC 0b00000000 +#define DSP_EA_POSTINC 0b00001000 +#define DSP_EA_POSTDEC1 0b00010000 +#define DSP_EA_POSTINC1 0b00011000 +#define DSP_EA_NOUPD 0b00100000 +#define DSP_EA_INDEX 0b00101000 +#define DSP_EA_PREDEC1 0b00111000 +#define DSP_EA_ABS 0b00110000 +#define DSP_EA_IMM 0b00110100 // Mnemonic table structure diff --git a/mach.c b/mach.c index 90c0412..3c7a30c 100644 --- a/mach.c +++ b/mach.c @@ -352,7 +352,7 @@ int m_lea(WORD inst, WORD siz) && ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED)) && ((a0exval > 0) && (a0exval <= 8))) { - inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg); + inst = 0b0101000001001000 | (((uint16_t)a0exval & 7) << 9) | (a0reg); D_word(inst); if (optim_warn_flag) @@ -468,7 +468,7 @@ int m_adda(WORD inst, WORD siz) if ((a0exval > 1) && (a0exval <= 8)) { // Immediate is between 1 and 8 so let's convert to addq - return m_addq(B16(01010000, 00000000), siz); + return m_addq(0b0101000000000000, siz); if (optim_warn_flag) warn("o8: adda/suba size(An),An converted to addq/subq #size,An"); @@ -494,7 +494,7 @@ int m_adda(WORD inst, WORD siz) int return_value; int temp_flag = optim_flags[OPT_LEA_ADDQ]; optim_flags[OPT_LEA_ADDQ] = 1; // Temporarily save switch state - return_value = m_lea(B16(01000001, 11011000), SIZW); + return_value = m_lea(0b0100000111011000, SIZW); optim_flags[OPT_LEA_ADDQ] = temp_flag; // Restore switch state if (optim_warn_flag) warn("o9: adda.w/l #x,Ay converted to lea x(Dy),Ay"); @@ -1164,7 +1164,7 @@ int m_clrd(WORD inst, WORD siz) inst |= a0reg; else { - inst = (a0reg << 9) | B16(01110000, 00000000); + inst = (a0reg << 9) | 0b0111000000000000; if (optim_warn_flag) warn("o7: clr.l Dx converted to moveq #0,Dx"); } @@ -1239,7 +1239,7 @@ int m_bfop(WORD inst, WORD siz) bfparam1 = bfval1 << 12; //D_word((inst | am0 | a0reg | am1 | a1reg)); - if (inst == B16(11101111, 11000000)) + if (inst == 0b1110111111000000) { // bfins special case D_word((inst | am1 | a1reg)); @@ -1252,7 +1252,7 @@ int m_bfop(WORD inst, WORD siz) ea0gen(siz); // Generate EA // Second instruction word - Dest register (if exists), Do, Offset, Dw, Width - if (inst == B16(11101111, 11000000)) + if (inst == 0b1110111111000000) { // bfins special case inst = bfparam1 | bfparam2; @@ -2206,7 +2206,7 @@ int m_pflusha(WORD inst, WORD siz) } else if (activecpu == CPU_68040) { - inst = B16(11110101, 00011000); + inst = 0b1111010100011000; D_word(inst); return OK; } @@ -2417,7 +2417,7 @@ int m_pflushr(WORD inst, WORD siz) ea1gen(siz); } - D_word(B16(10100000, 00000000)); + D_word(0b1010000000000000); return OK; } @@ -2795,7 +2795,7 @@ static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul) int m_fabs(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00011000, FPU_NOWARN); } @@ -2806,7 +2806,7 @@ int m_fsabs(WORD inst, WORD siz) { CHECKNO40; if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011000, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -2818,7 +2818,7 @@ int m_fsabs(WORD inst, WORD siz) int m_fdabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011100, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -2830,7 +2830,7 @@ int m_fdabs(WORD inst, WORD siz) int m_facos(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011100), FPU_FPSP); + return gen_fpu(inst, siz, 0b00011100, FPU_FPSP); } @@ -2840,7 +2840,7 @@ int m_facos(WORD inst, WORD siz) int m_fadd(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00100010, FPU_NOWARN); } @@ -2850,7 +2850,7 @@ int m_fadd(WORD inst, WORD siz) int m_fsadd(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100010, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -2862,7 +2862,7 @@ int m_fsadd(WORD inst, WORD siz) int m_fdadd(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100110, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -2874,7 +2874,7 @@ int m_fdadd(WORD inst, WORD siz) int m_fasin(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001100), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001100, FPU_FPSP); } @@ -2884,7 +2884,7 @@ int m_fasin(WORD inst, WORD siz) int m_fatan(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001010), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001010, FPU_FPSP); } @@ -2894,7 +2894,7 @@ int m_fatan(WORD inst, WORD siz) int m_fatanh(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001101), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001101, FPU_FPSP); } @@ -2904,7 +2904,7 @@ int m_fatanh(WORD inst, WORD siz) int m_fcmp(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00111000), FPU_FPSP); + return gen_fpu(inst, siz, 0b00111000, FPU_FPSP); } @@ -2914,7 +2914,7 @@ int m_fcmp(WORD inst, WORD siz) int m_fcos(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011101), FPU_FPSP); + return gen_fpu(inst, siz, 0b00011101, FPU_FPSP); } @@ -2924,7 +2924,7 @@ int m_fcos(WORD inst, WORD siz) int m_fcosh(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011001), FPU_FPSP); + return gen_fpu(inst, siz, 0b00011001, FPU_FPSP); } @@ -2975,7 +2975,7 @@ int m_fdbcc(WORD inst, WORD siz) int m_fdiv(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00100000, FPU_NOWARN); } @@ -2985,7 +2985,7 @@ int m_fdiv(WORD inst, WORD siz) int m_fsdiv(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100000, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -2997,7 +2997,7 @@ int m_fsdiv(WORD inst, WORD siz) int m_fddiv(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100100, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3009,7 +3009,7 @@ int m_fddiv(WORD inst, WORD siz) int m_fetox(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010000), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010000, FPU_FPSP); } @@ -3019,7 +3019,7 @@ int m_fetox(WORD inst, WORD siz) int m_fetoxm1(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001000), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001000, FPU_FPSP); } @@ -3029,7 +3029,7 @@ int m_fetoxm1(WORD inst, WORD siz) int m_fgetexp(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011110), FPU_FPSP); + return gen_fpu(inst, siz, 0b00011110, FPU_FPSP); } @@ -3039,7 +3039,7 @@ int m_fgetexp(WORD inst, WORD siz) int m_fgetman(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00011111), FPU_FPSP); + return gen_fpu(inst, siz, 0b00011111, FPU_FPSP); } @@ -3055,7 +3055,7 @@ int m_fint(WORD inst, WORD siz) if (activefpu == FPU_68040) warn("Instruction is emulated in 68040"); - return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00000001, FPU_NOWARN); } @@ -3071,7 +3071,7 @@ int m_fintrz(WORD inst, WORD siz) if (activefpu == FPU_68040) warn("Instruction is emulated in 68040"); - return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00000011, FPU_NOWARN); } @@ -3081,7 +3081,7 @@ int m_fintrz(WORD inst, WORD siz) int m_flog10(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010101), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010101, FPU_FPSP); } @@ -3091,7 +3091,7 @@ int m_flog10(WORD inst, WORD siz) int m_flog2(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010110), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010110, FPU_FPSP); } @@ -3101,7 +3101,7 @@ int m_flog2(WORD inst, WORD siz) int m_flogn(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010100), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010100, FPU_FPSP); } @@ -3111,7 +3111,7 @@ int m_flogn(WORD inst, WORD siz) int m_flognp1(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00000110), FPU_FPSP); + return gen_fpu(inst, siz, 0b00000110, FPU_FPSP); } @@ -3121,7 +3121,7 @@ int m_flognp1(WORD inst, WORD siz) int m_fmod(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100001), FPU_FPSP); + return gen_fpu(inst, siz, 0b00100001, FPU_FPSP); } @@ -3293,7 +3293,7 @@ int m_fsmove(WORD inst, WORD siz) if (!(activefpu & (FPU_68040 | FPU_68060))) return error("Unsupported in current FPU"); - return gen_fpu(inst, siz, B8(01100100), FPU_FPSP); + return gen_fpu(inst, siz, 0b01100100, FPU_FPSP); } @@ -3302,7 +3302,7 @@ int m_fdmove(WORD inst, WORD siz) if (!(activefpu & (FPU_68040 | FPU_68060))) return error("Unsupported in current FPU"); - return gen_fpu(inst, siz, B8(01100100), FPU_FPSP); + return gen_fpu(inst, siz, 0b01100100, FPU_FPSP); } @@ -3550,7 +3550,7 @@ fmovem_loop_2: int m_fmul(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00100011, FPU_NOWARN); } @@ -3560,7 +3560,7 @@ int m_fmul(WORD inst, WORD siz) int m_fsmul(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100011, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3572,7 +3572,7 @@ int m_fsmul(WORD inst, WORD siz) int m_fdmul(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01100111, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3588,10 +3588,10 @@ int m_fneg(WORD inst, WORD siz) if (am1 == AM_NONE) { a1reg = a0reg; - return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN); } - return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN); } @@ -3605,10 +3605,10 @@ int m_fsneg(WORD inst, WORD siz) if (am1 == AM_NONE) { a1reg = a0reg; - return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN); } - return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN); } return error("Unsupported in current FPU"); @@ -3625,10 +3625,10 @@ int m_fdneg(WORD inst, WORD siz) if (am1 == AM_NONE) { a1reg = a0reg; - return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN); } - return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN); } return error("Unsupported in current FPU"); @@ -3641,7 +3641,7 @@ int m_fdneg(WORD inst, WORD siz) int m_fnop(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00000000, FPU_NOWARN); } @@ -3651,7 +3651,7 @@ int m_fnop(WORD inst, WORD siz) int m_frem(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100101), FPU_FPSP); + return gen_fpu(inst, siz, 0b00100101, FPU_FPSP); } @@ -3661,7 +3661,7 @@ int m_frem(WORD inst, WORD siz) int m_fscale(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100110), FPU_FPSP); + return gen_fpu(inst, siz, 0b00100110, FPU_FPSP); } @@ -3694,7 +3694,7 @@ int m_fscc(WORD inst, WORD siz) int m_fsgldiv(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100100), FPU_FPSP); + return gen_fpu(inst, siz, 0b00100100, FPU_FPSP); } @@ -3704,7 +3704,7 @@ int m_fsgldiv(WORD inst, WORD siz) int m_fsglmul(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00100111), FPU_FPSP); + return gen_fpu(inst, siz, 0b00100111, FPU_FPSP); } @@ -3714,7 +3714,7 @@ int m_fsglmul(WORD inst, WORD siz) int m_fsin(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001110), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001110, FPU_FPSP); } @@ -3732,7 +3732,7 @@ int m_fsincos(WORD inst, WORD siz) a2reg = a1reg; a1reg = temp; - if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK) + if (gen_fpu(inst, siz, 0b00110000, FPU_FPSP) == OK) { chptr[-1] |= a2reg; return OK; @@ -3748,7 +3748,7 @@ int m_fsincos(WORD inst, WORD siz) int m_fsinh(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00000010), FPU_FPSP); + return gen_fpu(inst, siz, 0b00000010, FPU_FPSP); } @@ -3758,7 +3758,7 @@ int m_fsinh(WORD inst, WORD siz) int m_fsqrt(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00000100, FPU_NOWARN); } @@ -3768,7 +3768,7 @@ int m_fsqrt(WORD inst, WORD siz) int m_fsfsqrt(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01000001, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3780,7 +3780,7 @@ int m_fsfsqrt(WORD inst, WORD siz) int m_fdfsqrt(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01000101, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3792,7 +3792,7 @@ int m_fdfsqrt(WORD inst, WORD siz) int m_fsub(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00101000, FPU_NOWARN); } @@ -3802,7 +3802,7 @@ int m_fsub(WORD inst, WORD siz) int m_fsfsub(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01101000, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3814,7 +3814,7 @@ int m_fsfsub(WORD inst, WORD siz) int m_fdsub(WORD inst, WORD siz) { if (activefpu & (FPU_68040 | FPU_68060)) - return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN); + return gen_fpu(inst, siz, 0b01101100, FPU_NOWARN); return error("Unsupported in current FPU"); } @@ -3826,7 +3826,7 @@ int m_fdsub(WORD inst, WORD siz) int m_ftan(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001111), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001111, FPU_FPSP); } @@ -3836,7 +3836,7 @@ int m_ftan(WORD inst, WORD siz) int m_ftanh(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00001001), FPU_FPSP); + return gen_fpu(inst, siz, 0b00001001, FPU_FPSP); } @@ -3846,7 +3846,7 @@ int m_ftanh(WORD inst, WORD siz) int m_ftentox(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010010), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010010, FPU_FPSP); } @@ -3897,7 +3897,7 @@ int m_ftrapcc(WORD inst, WORD siz) int m_ftst(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN); + return gen_fpu(inst, siz, 0b00111010, FPU_NOWARN); } @@ -3907,7 +3907,7 @@ int m_ftst(WORD inst, WORD siz) int m_ftwotox(WORD inst, WORD siz) { CHECKNOFPU; - return gen_fpu(inst, siz, B8(00010001), FPU_FPSP); + return gen_fpu(inst, siz, 0b00010001, FPU_FPSP); } @@ -3924,7 +3924,7 @@ int m_ftwotox(WORD inst, WORD siz) int m_lpstop(WORD inst, WORD siz) { CHECKNO60; - D_word(B16(00000001, 11000000)); + D_word(0b0000000111000000); if (a0exattr & DEFINED) { diff --git a/rmac.h b/rmac.h index 2ca16c2..d03d010 100644 --- a/rmac.h +++ b/rmac.h @@ -264,29 +264,6 @@ PTR #define EQUATEDCC 0x0020 #define UNDEF_CC 0x0040 -// Construct binary constants at compile time -// Code by Tom Torfs - -// Helper macros -#define HEX__(n) 0x##n##LU -#define B8__(x) \ - ((x&0x0000000FLU)?1:0) \ -+((x&0x000000F0LU)?2:0) \ -+((x&0x00000F00LU)?4:0) \ -+((x&0x0000F000LU)?8:0) \ -+((x&0x000F0000LU)?16:0) \ -+((x&0x00F00000LU)?32:0) \ -+((x&0x0F000000LU)?64:0) \ -+((x&0xF0000000LU)?128:0) - -// User macros -#define B8(d) ((uint8_t)B8__(HEX__(d))) -#define B16(dmsb,dlsb) (((uint16_t)B8(dmsb)<<8) + B8(dlsb)) -#define B32(dmsb,db2,db3,dlsb) (((uint32_t)B8(dmsb)<<24) \ -+ ((uint32_t)B8(db2)<<16) \ -+ ((uint32_t)B8(db3)<<8) \ -+ B8(dlsb)) - // Optimisation defines enum { -- 2.33.0.windows.1 From 3d40c7ba37d06772d9ba33b8bad3dc6a9c64ae1e Mon Sep 17 00:00:00 2001 From: ggn Date: Thu, 24 Mar 2022 13:28:09 +0200 Subject: [PATCH 2/4] Fix for #159: Split register sets according to architecture into different tables so they don't clash with label/symbol names. Modified tokeniser to use different tables when scanning for registers --- 56kregs.tab | 62 +++++++++++++ 6502.c | 23 +++-- 6502regs.tab | 3 + 68kregs.tab | 71 ++++++++++++++ amode.c | 24 ++--- direct.c | 77 ++++++++++----- docs/rmac.rst | 5 - dsp56k_amode.c | 248 ++++++++++++++++++++++++------------------------- dsp56k_mach.c | 68 +++++++------- kw.tab | 158 ------------------------------- mach.c | 112 +++++++++++----------- makefile | 28 ++++-- maketabs.bat | 36 ++++++- parmode.h | 58 ++++++------ procln.c | 12 +-- riscasm.c | 25 ++--- riscregs.tab | 35 +++++++ rmac.c | 13 +++ rmac.h | 4 + sect.c | 9 +- token.c | 95 +++++++++++-------- unary.tab | 11 +++ 22 files changed, 659 insertions(+), 518 deletions(-) create mode 100644 56kregs.tab create mode 100644 6502regs.tab create mode 100644 68kregs.tab create mode 100644 riscregs.tab create mode 100644 unary.tab diff --git a/56kregs.tab b/56kregs.tab new file mode 100644 index 0000000..6e45d56 --- /dev/null +++ b/56kregs.tab @@ -0,0 +1,62 @@ +a0 136 +a1 137 +a2 138 + +sp 143 +pc 145 +sr 146 +ccr 147 + +r0 151 +r1 152 +r2 153 +r3 154 +r4 155 +r5 156 +r6 157 +r7 158 + +x0 260 +x1 261 +y0 262 +y1 263 +b0 265 +b2 267 +b1 269 +a 270 +b 271 +n0 280 +n1 281 +n2 282 +n3 283 +n4 284 +n5 285 +n6 286 +n7 287 +m0 288 +m1 289 +m2 290 +m3 291 +m4 292 +m5 293 +m6 294 +m7 295 + +mr 304 +omr 305 +la 306 +lc 307 +ssh 308 +ssl 309 +ss 310 + +l 302 +p 303 + +a10 312 +b10 313 +x 314 +y 315 +ab 318 +ba 319 + diff --git a/6502.c b/6502.c index d478e3a..89029c1 100644 --- a/6502.c +++ b/6502.c @@ -21,8 +21,9 @@ #include "sect.h" #include "token.h" -#define DEF_KW -#include "kwtab.h" +#define DEF_REG65 +#define DECL_REG65 +#include "6502regs.h" #define UPSEG_SIZE 0x10010L // size of 6502 code buffer, 64K+16bytes @@ -238,6 +239,10 @@ int d_6502() { SaveSection(); // Save curent section SwitchSection(M6502); // Switch to 6502 section + regbase = reg65base; // Update register DFA tables + regtab = reg65tab; + regcheck = reg65check; + regaccept = reg65accept; return 0; } @@ -263,7 +268,7 @@ void m6502cg(int op) amode = A65_IMPL; break; - case KW_A: + case REG65_A: if (tok[1] != EOL) goto badmode; @@ -307,7 +312,7 @@ void m6502cg(int op) tok++; amode = A65_INDY; - if (tok[0] != KW_Y) + if (tok[0] != REG65_Y) goto badmode; tok++; @@ -315,7 +320,7 @@ void m6502cg(int op) else amode = A65_IND; } - else if ((tok[0] == ',') && (tok[1] == KW_X) && (tok[2] == ')')) + else if ((tok[0] == ',') && (tok[1] == REG65_X) && (tok[2] == ')')) { // (foo,x) tok += 3; @@ -341,9 +346,9 @@ void m6502cg(int op) if ((tok[1] != ')') || (tok[2] != EOL)) goto badmode; - if (tok[0] == KW_X) + if (tok[0] == REG65_X) amode = A65_INDX; - else if (tok[0] == KW_Y) + else if (tok[0] == REG65_Y) amode = A65_INDY; else goto badmode; @@ -373,12 +378,12 @@ void m6502cg(int op) { tok++; - if (tok[0] == KW_X) + if (tok[0] == REG65_X) { tok++; amode = A65_ABSX; } - else if (tok[0] == KW_Y) + else if (tok[0] == REG65_Y) { tok++; amode = A65_ABSY; diff --git a/6502regs.tab b/6502regs.tab new file mode 100644 index 0000000..fa3579a --- /dev/null +++ b/6502regs.tab @@ -0,0 +1,3 @@ +a 270 +x 314 +y 315 diff --git a/68kregs.tab b/68kregs.tab new file mode 100644 index 0000000..78dc44a --- /dev/null +++ b/68kregs.tab @@ -0,0 +1,71 @@ +d0 128 +d1 129 +d2 130 +d3 131 +d4 132 +d5 133 +d6 134 +d7 135 + +a0 136 +a1 137 +a2 138 +a3 139 +a4 140 +a5 141 +a6 142 +a7 143 + +sp 143 +usp 184 +ssp 144 +pc 145 +sr 146 +ccr 147 + +ic40 185 +dc40 186 +bc40 187 + +sfc 188 +dfc 189 +vbr 191 + +cacr 192 +caar 193 +msp 194 +isp 195 + +tc 196 +itt0 197 +itt1 198 +dtt0 199 +dtt1 200 +mmusr 201 +psr 201 +urp 202 +srp 203 + +iacr0 204 +iacr1 205 +dacr0 206 +dacr1 207 + +tt0 208 +tt1 209 + +crp 210 + +fpiar 220 +fpsr 221 +fpcr 222 + +fp0 224 +fp1 225 +fp2 226 +fp3 227 +fp4 228 +fp5 229 +fp6 230 +fp7 231 + diff --git a/amode.c b/amode.c index 7a7c7ba..6fd3538 100644 --- a/amode.c +++ b/amode.c @@ -15,8 +15,8 @@ #include "sect.h" #include "token.h" -#define DEF_KW -#include "kwtab.h" +#define DEF_REG68 +#include "68kregs.h" #define DEF_MN #include "mntab.h" @@ -171,9 +171,9 @@ int amode(int acount) // TODO: protect this from combinations like Dx:FPx etc :) tok++; //eat the colon - if ((*tok >= KW_D0) && (*tok <= KW_D7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) a2reg = (*tok++) & 7; - else if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + else if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) a2reg = (*tok++) & 7; else return error("a data or FPU register must follow a :"); @@ -211,7 +211,7 @@ int reglist(WORD * a_rmask) for(;;) { - if ((*tok >= KW_D0) && (*tok <= KW_A7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_A7)) r = *tok++ & 0x0F; else break; @@ -220,7 +220,7 @@ int reglist(WORD * a_rmask) { tok++; - if ((*tok >= KW_D0) && (*tok <= KW_A7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_A7)) cnt = *tok++ & 0x0F; else return error("register list syntax"); @@ -263,7 +263,7 @@ int fpu_reglist_left(WORD * a_rmask) for(;;) { - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) r = *tok++ & 0x07; else break; @@ -272,7 +272,7 @@ int fpu_reglist_left(WORD * a_rmask) { tok++; - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) cnt = *tok++ & 0x07; else return error("register list syntax"); @@ -314,7 +314,7 @@ int fpu_reglist_right(WORD * a_rmask) for(;;) { - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) r = *tok++ & 0x07; else break; @@ -323,7 +323,7 @@ int fpu_reglist_right(WORD * a_rmask) { tok++; - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) cnt = *tok++ & 0x07; else return error("register list syntax"); @@ -385,7 +385,7 @@ int Check030Bitfield(void) // Do=0, offset=immediate - shift it to place bfparam1 = (0 << 11); } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { // Do=1, offset=data register - shift it to place bfparam1 = (1 << 11); @@ -428,7 +428,7 @@ int Check030Bitfield(void) // Do=0, offset=immediate - shift it to place bfparam2 = (0 << 5); } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { // Do=1, offset=data register - shift it to place bfval2 = (*(int *)tok - 128); diff --git a/direct.c b/direct.c index fc1710e..8d2ee33 100644 --- a/direct.c +++ b/direct.c @@ -25,7 +25,15 @@ #define DEF_KW #include "kwtab.h" - +#define DEF_REG56 +#define DECL_REG56 +#include "56kregs.h" +#define DEF_REG68 +#define DECL_REG68 +#include "68kregs.h" +#define DEF_REGRISC +#define DECL_REGRISC +#include "riscregs.h" TOKEN exprbuf[128]; // Expression buffer SYM * symbolPtr[1000000]; // Symbol pointers table @@ -281,22 +289,22 @@ int d_org(void) switch (tok[0]) { - case KW_X: + case REG56_X: dsp_currentorg->memtype = ORG_X; sectionToSwitch = M56001X; break; - case KW_Y: + case REG56_Y: dsp_currentorg->memtype = ORG_Y; sectionToSwitch = M56001Y; break; - case KW_P: + case REG56_P: dsp_currentorg->memtype = ORG_P; sectionToSwitch = M56001P; break; - case KW_L: + case REG56_L: dsp_currentorg->memtype = ORG_L; sectionToSwitch = M56001L; break; @@ -396,15 +404,16 @@ int d_print(void) formatting = 1; // "X" & "L" get tokenized now... :-/ Probably should look into preventing this kind of thing from happening (was added with DSP56K code) - if ((tok[1] != SYMBOL) && (tok[1] != KW_L) && (tok[1] != KW_X)) + // Note (ggn): This is now much less severe as it's localised for 56k only + if ((tok[1] != SYMBOL) && (tok[1] != REG56_L) && (tok[1] != REG56_X)) goto token_err; - if (tok[1] == KW_L) + if (tok[1] == REG56_L) { wordlong = 1; tok += 2; } - else if (tok[1] == KW_X) + else if (tok[1] == REG56_X) { outtype = 0; tok += 2; @@ -1844,6 +1853,10 @@ int d_68000(void) SaveSection(); SwitchSection(TEXT); activecpu = CPU_68000; + regbase = reg68base; // Update register DFA tables + regtab = reg68tab; + regcheck = reg68check; + regaccept = reg68accept; return 0; } @@ -1899,8 +1912,11 @@ int d_68060(void) // int d_68881(void) { - //d_68000(); activefpu = FPU_68881; + regbase = reg68base; // Update register DFA tables + regtab = reg68tab; + regcheck = reg68check; + regaccept = reg68accept; return 0; } @@ -1910,8 +1926,11 @@ int d_68881(void) // int d_68882(void) { - //d_68000(); activefpu = FPU_68882; + regbase = reg68base; // Update register DFA tables + regtab = reg68tab; + regcheck = reg68check; + regaccept = reg68accept; return 0; } @@ -1938,6 +1957,10 @@ int d_56001(void) if ((obj_format == LOD) || (obj_format == P56)) SwitchSection(M56001P); + regbase = reg56base; // Update register DFA tables + regtab = reg56tab; + regcheck = reg56check; + regaccept = reg56accept; return 0; } @@ -1964,6 +1987,11 @@ int d_gpu(void) rdsp = 0; // Unset DSP assembly robjproc = 0; // Unset OP assembly dsp56001 = 0; // Unset 56001 assembly + + regbase = regriscbase; // Update register DFA tables + regtab = regrisctab; + regcheck = regrisccheck; + regaccept = regriscaccept; return 0; } @@ -1990,6 +2018,11 @@ int d_dsp(void) rgpu = 0; // Unset GPU assembly robjproc = 0; // Unset OP assembly dsp56001 = 0; // Unset 56001 assembly + + regbase = regriscbase; // Update register DFA tables + regtab = regrisctab; + regcheck = regrisccheck; + regaccept = regriscaccept; return 0; } @@ -2068,7 +2101,7 @@ int d_cargs(void) eval += 2; } - else if (*tok >= KW_D0 && *tok <= KW_A7) + else if (*tok >= REG68_D0 && *tok <= REG68_A7) { if (reglist(&rlist) < 0) return 0; @@ -2083,13 +2116,13 @@ int d_cargs(void) { switch ((int)*tok) { - case KW_USP: - case KW_SSP: - case KW_PC: + case REG68_USP: + case REG68_SSP: + case REG68_PC: eval += 2; // FALLTHROUGH - case KW_SR: - case KW_CCR: + case REG68_SR: + case REG68_CCR: eval += 2; tok++; break; @@ -2200,7 +2233,7 @@ int d_cstruct(void) tok++; } - else if (*tok >= KW_D0 && *tok <= KW_A7) + else if (*tok >= REG68_D0 && *tok <= REG68_A7) { if (reglist(&rlist) < 0) return 0; @@ -2215,13 +2248,13 @@ int d_cstruct(void) { switch ((int)*tok) { - case KW_USP: - case KW_SSP: - case KW_PC: + case REG68_USP: + case REG68_SSP: + case REG68_PC: eval += 2; // FALLTHROUGH - case KW_SR: - case KW_CCR: + case REG68_SR: + case REG68_CCR: eval += 2; tok++; break; diff --git a/docs/rmac.rst b/docs/rmac.rst index cb1d4f8..23acb51 100644 --- a/docs/rmac.rst +++ b/docs/rmac.rst @@ -2429,11 +2429,6 @@ order, along with a short description of what may have caused the problem. The expression has an undefined value because of a forward reference, or an undefined or external symbol. -**unimplemented addressing mode** - - You tried to use 68020 "square-bracket" notation for a 68020 addressing mode. - RMAC does not support 68020 addressing modes. - **unimplemented directive** You have found a directive that didn't appear in the documentation. It doesn't diff --git a/dsp56k_amode.c b/dsp56k_amode.c index 22ed0e1..7a7ee3d 100644 --- a/dsp56k_amode.c +++ b/dsp56k_amode.c @@ -15,10 +15,10 @@ #include "sect.h" #include "math.h" -#define DEF_KW -#include "kwtab.h" #define DEF_MN #include "mntab.h" +#define DEF_REG56 +#include "56kregs.h" // Address-mode information int dsp_am0; // Addressing mode @@ -154,7 +154,7 @@ enum // static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnEXVAL, WORD * AnEXATTR, SYM ** AnESYM, LONG *memspace, LONG *perspace, const int operand) { - if (*tok == KW_A || *tok == KW_B) + if (*tok == REG56_A || *tok == REG56_B) { *am = M_ACC56; *areg = *tok++; @@ -222,13 +222,13 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE return OK; } - else if (*tok >= KW_X0 && *tok <= KW_Y1) + else if (*tok >= REG56_X0 && *tok <= REG56_Y1) { *am = M_ALU24; *areg = *tok++; return OK; } - else if (*tok == KW_X && *(tok + 1) == ':') + else if (*tok == REG56_X && *(tok + 1) == ':') { tok = tok + 2; @@ -373,7 +373,7 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE else return ERROR; } - else if (*tok == KW_Y && *(tok + 1) == ':') + else if (*tok == REG56_Y && *(tok + 1) == ':') { tok = tok + 2; @@ -531,44 +531,44 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE return ERROR; // TODO: add absolute address checks } - else if ((*tok >= KW_X) && (*tok <= KW_Y)) + else if ((*tok >= REG56_X) && (*tok <= REG56_Y)) { *am = M_INP48; *areg = *tok++; return OK; } - else if ((*tok >= KW_M0) && (*tok <= KW_M7)) + else if ((*tok >= REG56_M0) && (*tok <= REG56_M7)) { *am = M_DSPM; *areg = (*tok++) & 7; return OK; } - else if ((*tok >= KW_R0) && (*tok <= KW_R7)) + else if ((*tok >= REG56_R0) && (*tok <= REG56_R7)) { *am = M_DSPR; - *areg = (*tok++) - KW_R0; + *areg = (*tok++) - REG56_R0; return OK; } - else if ((*tok >= KW_N0) && (*tok <= KW_N7)) + else if ((*tok >= REG56_N0) && (*tok <= REG56_N7)) { *am = M_DSPN; *areg = (*tok++) & 7; return OK; } - else if ((*tok == KW_A0) || (*tok == KW_A1) || (*tok == KW_B0) - || (*tok == KW_B1)) + else if ((*tok == REG56_A0) || (*tok == REG56_A1) || (*tok == REG56_B0) + || (*tok == REG56_B1)) { *am = M_ACC24; *areg = *tok++; return OK; } - else if ((*tok == KW_A2) || (*tok == KW_B2)) + else if ((*tok == REG56_A2) || (*tok == REG56_B2)) { *am = M_ACC8; *areg = *tok++; return OK; } - else if ((*tok == '-') && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1)) + else if ((*tok == '-') && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1)) { // '-X0', '-Y0', '-X1' or '-Y1', used in multiplications tok++; @@ -582,7 +582,7 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE dsp_k = 1 << 2; return OK; } - else if (*tok == '+' && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1)) + else if (*tok == '+' && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1)) { // '+X0', '+Y0', '+X1' or '+Y1', used in multiplications tok++; @@ -621,7 +621,7 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE // TODO: add absolute address checks return error("internal assembler error: parmode checking for '(' and '-' does not have absolute address checks yet!"); } - else if (*tok == KW_P && *(tok + 1) == ':') + else if (*tok == REG56_P && *(tok + 1) == ':') { tok = tok + 2; @@ -741,7 +741,7 @@ static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnE *areg = DSP_EA_ABS; return OK; } - else if (*tok == KW_PC || *tok == KW_CCR || *tok == KW_SR || *tok == KW_SP || (*tok >= KW_MR&&*tok <= KW_SS)) + else if (*tok == REG56_PC || *tok == REG56_CCR || *tok == REG56_SR || *tok == REG56_SP || (*tok >= REG56_MR&&*tok <= REG56_SS)) { *areg = *tok++; *am = M_DSPPCU; @@ -886,12 +886,12 @@ int dsp_amode(int maxea) // static inline int SDreg(int reg) { - if (reg >= KW_X0 && reg <= KW_N7) + if (reg >= REG56_X0 && reg <= REG56_N7) return reg & 0xFF; - else if (reg >= KW_A0&® <= KW_A2) + else if (reg >= REG56_A0&® <= REG56_A2) return (8 >> (reg & 7)) | 8; - else //if (reg>=KW_R0&®<=KW_R7) - return reg - KW_R0 + 16; + else //if (reg>=REG56_R0&®<=REG56_R7) + return reg - REG56_R0 + 16; // Handy map for the above: // (values are of course taken from keytab) // Register | Value | Return value @@ -954,10 +954,10 @@ static inline LONG check_x_y(LONG ea1, LONG S1) // Check for D1 switch (K_D1 = *tok++) { - case KW_X0: D1 = 0 << 10; break; - case KW_X1: D1 = 1 << 10; break; - case KW_A: D1 = 2 << 10; break; - case KW_B: D1 = 3 << 10; break; + case REG56_X0: D1 = 0 << 10; break; + case REG56_X1: D1 = 1 << 10; break; + case REG56_A: D1 = 2 << 10; break; + case REG56_B: D1 = 3 << 10; break; default: return error("unrecognised X:Y: parallel move syntax: expected x0, x1, a or b after 'X:eax,'"); } } @@ -976,7 +976,7 @@ static inline LONG check_x_y(LONG ea1, LONG S1) } } - if (*tok == KW_Y) + if (*tok == REG56_Y) { tok++; // 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2' @@ -985,9 +985,9 @@ static inline LONG check_x_y(LONG ea1, LONG S1) if (*tok++ == '(') { - if (*tok >= KW_R0 && *tok <= KW_R7) + if (*tok >= REG56_R0 && *tok <= REG56_R7) { - ea2 = (*tok++ - KW_R0); + ea2 = (*tok++ - REG56_R0); if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4)) return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea Y:eay,D2'"); @@ -1012,7 +1012,7 @@ static inline LONG check_x_y(LONG ea1, LONG S1) ea2 = 3 << 12; tok++; } - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)+Nn if ((*tok++ & 7) != ea2) @@ -1048,10 +1048,10 @@ static inline LONG check_x_y(LONG ea1, LONG S1) switch (K_D2 = *tok++) { - case KW_Y0: D2 = 0 << 8; break; - case KW_Y1: D2 = 1 << 8; break; - case KW_A: D2 = 2 << 8; break; - case KW_B: D2 = 3 << 8; break; + case REG56_Y0: D2 = 0 << 8; break; + case REG56_Y1: D2 = 1 << 8; break; + case REG56_A: D2 = 2 << 8; break; + case REG56_B: D2 = 3 << 8; break; default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'"); } @@ -1069,22 +1069,22 @@ static inline LONG check_x_y(LONG ea1, LONG S1) else return error("unrecognised X:Y: parallel move syntax: expected '(Rn)', '(Rn)+', '(Rn)-', '(Rn)+Nn' after 'X:ea,D1/S1,X:ea Y:'"); } - else if (*tok == KW_Y0 || *tok == KW_Y1 || *tok == KW_A || *tok == KW_B) + else if (*tok == REG56_Y0 || *tok == REG56_Y1 || *tok == REG56_A || *tok == REG56_B) { // 'X:eax,D1 S2,Y:eay' 'S1,X:eax1 S2,Y:eay' switch (*tok++) { - case KW_Y0: S2 = 0 << 8; break; - case KW_Y1: S2 = 1 << 8; break; - case KW_A: S2 = 2 << 8; break; - case KW_B: S2 = 3 << 8; break; + case REG56_Y0: S2 = 0 << 8; break; + case REG56_Y1: S2 = 1 << 8; break; + case REG56_A: S2 = 2 << 8; break; + case REG56_B: S2 = 3 << 8; break; default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'"); } if (*tok++ != ',') return error("unrecognised X:Y: parallel move syntax: expected ',' after 'X:ea,D1/S1,X:ea S2'"); - if (*tok++ == KW_Y) + if (*tok++ == REG56_Y) { // 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2' if (*tok++ != ':') @@ -1092,9 +1092,9 @@ static inline LONG check_x_y(LONG ea1, LONG S1) if (*tok++ == '(') { - if (*tok >= KW_R0 && *tok <= KW_R7) + if (*tok >= REG56_R0 && *tok <= REG56_R7) { - ea2 = (*tok++ - KW_R0); + ea2 = (*tok++ - REG56_R0); if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4)) return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea S2,Y:eay'"); @@ -1115,7 +1115,7 @@ static inline LONG check_x_y(LONG ea1, LONG S1) if (*tok == EOL) // (Rn)+ ea2 = 3 << 12; - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)+Nn if ((*tok++ & 7) != ea2) @@ -1198,7 +1198,7 @@ static inline LONG parse_x(const int W, LONG inst, const LONG S1, const int chec { x_checkea_right: // 'S1,X:ea S2,D2', 'A,X:ea X0,A', 'B,X:ea X0,B', 'S1,X:eax Y:eay,D2', 'S1,X:eax S2,Y:eay' - if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_A) + if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_A) { // 'A,X:ea X0,A' if (ea1 == DSP_EA_ABS) @@ -1216,7 +1216,7 @@ x_checkea_right: inst = 0b0000100000000000 | ea1 | (0 << 8); return inst; } - else if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_B) + else if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_B) { // 'B,X:ea X0,B' if (ea1 == DSP_EA_ABS) @@ -1234,7 +1234,7 @@ x_checkea_right: inst = 0b0000100100000000 | ea1 | (1 << 8); return inst; } - else if (*tok == KW_A || *tok == KW_B) + else if (*tok == REG56_A || *tok == REG56_B) { // 'S1,X:ea S2,D2', 'S1,X:eax S2,Y:eay' switch (S1) @@ -1246,7 +1246,7 @@ x_checkea_right: default: return error("unrecognised X:R parallel move syntax: S1 can only be x0, x1, a or b in 'S1,X:ea S2,D2'"); } - if (tok[1] == ',' && tok[2] == KW_Y) + if (tok[1] == ',' && tok[2] == REG56_Y) { // 'S1,X:eax S2,Y:eay' return check_x_y(ea1, S1); @@ -1258,17 +1258,17 @@ x_checkea_right: switch (*tok++) { - case KW_A: S2 = 0 << 9; break; - case KW_B: S2 = 1 << 9; break; + case REG56_A: S2 = 0 << 9; break; + case REG56_B: S2 = 1 << 9; break; default: return error("unrecognised X:R parallel move syntax: expected a or b after 'S1,X:eax'"); } if (*tok++ != ',') return error("unrecognised X:R parallel move syntax: expected ',' after 'S1,X:eax S2'"); - if (*tok == KW_Y0 || *tok == KW_Y1) + if (*tok == REG56_Y0 || *tok == REG56_Y1) { - if (*tok++ == KW_Y0) + if (*tok++ == REG56_Y0) D2 = 0 << 8; else D2 = 1 << 8; @@ -1283,12 +1283,12 @@ x_checkea_right: else return error("unrecognised X:R parallel move syntax: expected y0 or y1 after 'X:eax,D1 S2,'"); } - else if (*tok == KW_Y) + else if (*tok == REG56_Y) { // 'S1,X:eax Y:eay,D2' return check_x_y(ea1, S1); } - else if (*tok == KW_Y0 || *tok == KW_Y1) + else if (*tok == REG56_Y0 || *tok == REG56_Y1) { // 'S1,X:eax S2,Y:eay' return check_x_y(ea1, S1); @@ -1317,7 +1317,7 @@ x_check_immed: // It might be X:aa but we're not 100% sure yet. // If it is, the only possible syntax here is 'X:aa,D'. // So check ahead to see if EOL follows D, then we're good to go. - if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL) + if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL) { // Yup, we're good to go - 'X:aa,D' it is tok++; @@ -1356,7 +1356,7 @@ x_check_immed: if (*tok++ != ',') return error("unrecognised X: parallel move syntax: expected ',' after 'X:ea'"); - if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) + if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) { D1 = SDreg(*tok++); @@ -1375,14 +1375,14 @@ x_check_immed: else { // 'X:ea,D1 S2,D2' - if (*tok == KW_A || *tok == KW_B) + if (*tok == REG56_A || *tok == REG56_B) { S2 = SDreg(*tok++); if (*tok++ != ',') return error("unrecognised X:R parallel move syntax: expected comma after X:ea,D1 S2"); - if (*tok == KW_Y0 || *tok == KW_Y1) + if (*tok == REG56_Y0 || *tok == REG56_Y1) { D2 = SDreg(*tok++); @@ -1480,7 +1480,7 @@ x_gotea1: // It might be 'X:(Rn..)..,D' but we're not 100% sure yet. // If it is, the only possible syntax here is 'X:ea,D'. // So check ahead to see if EOL follows D, then we're good to go. - if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL) + if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL) { //'X:ea,D' D1 = SDreg(*tok++); @@ -1509,32 +1509,32 @@ x_gotea1: // 'X:eax,D1 Y:eay,D2', 'X:eax,D1 S2,Y:eay' or 'X:ea,D1 S2,D2' // Check ahead for S2,D2 - if that's true then we have 'X:ea,D1 S2,D2' - if ((*tok == KW_X0 || *tok == KW_X1 || *tok == KW_A || *tok == KW_B) && (*(tok + 1) == KW_A || *(tok + 1) == KW_B) && (*(tok + 2) == ',') && (*(tok + 3) == KW_Y0 || (*(tok + 3) == KW_Y1))) + if ((*tok == REG56_X0 || *tok == REG56_X1 || *tok == REG56_A || *tok == REG56_B) && (*(tok + 1) == REG56_A || *(tok + 1) == REG56_B) && (*(tok + 2) == ',') && (*(tok + 3) == REG56_Y0 || (*(tok + 3) == REG56_Y1))) { // 'X:ea,D1 S2,D2' // Check if D1 is x0, x1, a or b switch (*tok++) { - case KW_X0: D1 = 0 << 10; break; - case KW_X1: D1 = 1 << 10; break; - case KW_A: D1 = 2 << 10; break; - case KW_B: D1 = 3 << 10; break; + case REG56_X0: D1 = 0 << 10; break; + case REG56_X1: D1 = 1 << 10; break; + case REG56_A: D1 = 2 << 10; break; + case REG56_B: D1 = 3 << 10; break; default: return error("unrecognised X:R parallel move syntax: expected x0, x1, a or b after 'X:eax,'"); } switch (*tok++) { - case KW_A: S2 = 0 << 9; break; - case KW_B: S2 = 1 << 9; break; + case REG56_A: S2 = 0 << 9; break; + case REG56_B: S2 = 1 << 9; break; default: return error("unrecognised X:R parallel move syntax: expected a or b after 'X:eax,D1 '"); } if (*tok++ != ',') return error("unrecognised X:R parallel move syntax: expected ',' after 'X:eax,D1 S2'"); - if (*tok == KW_Y0 || *tok == KW_Y1) + if (*tok == REG56_Y0 || *tok == REG56_Y1) { - if (*tok++ == KW_Y0) + if (*tok++ == REG56_Y0) D2 = 0 << 8; else D2 = 1 << 8; @@ -1697,7 +1697,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) return inst; } - if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL) + if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL) { // Yup, we're good to go - 'Y:aa,D' it is tok++; @@ -1726,7 +1726,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) if (D1 == 0 && S1 == 0) { // 'Y:ea,D' - if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) + if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) { D1 = SDreg(*tok++); @@ -1746,7 +1746,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) else { // 'S1,D1 Y:ea,D2' - if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1) + if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1) { D2 = SDreg(*tok++); inst |= ea1; @@ -1838,10 +1838,10 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) switch (*tok++) { - case KW_Y0: D2 = 0 << 8; break; - case KW_Y1: D2 = 1 << 8; break; - case KW_A: D2 = 2 << 8; break; - case KW_B: D2 = 3 << 8; break; + case REG56_Y0: D2 = 0 << 8; break; + case REG56_Y1: D2 = 1 << 8; break; + case REG56_A: D2 = 2 << 8; break; + case REG56_B: D2 = 3 << 8; break; default: return error("unrecognised R:Y parallel move syntax: D2 can only be y0, y1, a or b after 'S1,D1 Y:ea'"); } @@ -1857,7 +1857,7 @@ static inline LONG parse_y(LONG inst, LONG S1, LONG D1, LONG S2) // It might be 'Y:(Rn..)..,D' but we're not 100% sure yet. // If it is, the only possible syntax here is 'Y:ea,D'. // So check ahead to see if EOL follows D, then we're good to go. - if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL) + if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL) { //'Y:ea,D' D1 = SDreg(*tok++); @@ -2020,9 +2020,9 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) if (dspImmedEXVAL < 0x40 && force_imm != NUM_FORCE_LONG) { // 'S,L:aa' - if (S1 == KW_A) + if (S1 == REG56_A) S1 = 4; - else if (S1 == KW_B) + else if (S1 == REG56_B) S1 = 5; else S1 &= 7; @@ -2035,9 +2035,9 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) else { // 'S,L:ea' - if (S1 == KW_A) + if (S1 == REG56_A) S1 = 4; - else if (S1 == KW_B) + else if (S1 == REG56_B) S1 = 5; else S1 &= 7; @@ -2057,7 +2057,7 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) return error("unrecognised L: parallel move syntax: expected ',' after 'L:ea/L:aa'"); // Check for allowed registers for D (a0, b0, x, y, a, b, ab or ba) - if (!((*tok >= KW_A10 && *(tok + 1) <= KW_BA) || (*tok >= KW_A && *tok <= KW_B))) + if (!((*tok >= REG56_A10 && *(tok + 1) <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B))) return error("unrecognised L: parallel move syntax: expected a0, b0, x, y, a, b, ab or ba after 'L:ea/L:aa'"); if (dspImmedEXVAL < (1 << 6) && (dspImmedEXATTR&DEFINED)) @@ -2066,9 +2066,9 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) l_aa: immreg = *tok++; - if (immreg == KW_A) + if (immreg == REG56_A) immreg = 4; - else if (immreg == KW_B) + else if (immreg == REG56_B) immreg = 5; else immreg &= 7; @@ -2093,9 +2093,9 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) // 'L:ea,D' D1 = *tok++; - if (D1 == KW_A) + if (D1 == REG56_A) D1 = 4; - else if (D1 == KW_B) + else if (D1 == REG56_B) D1 = 5; else D1 &= 7; @@ -2145,9 +2145,9 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) // 'S,L:ea' inst = 0b0100000001000000; - if (S1 == KW_A) + if (S1 == REG56_A) S1 = 4; - else if (S1 == KW_B) + else if (S1 == REG56_B) S1 = 5; else S1 &= 7; @@ -2162,14 +2162,14 @@ static inline LONG parse_l(const int W, LONG inst, LONG S1) // It might be 'L:(Rn..)..,D' but we're not 100% sure yet. // If it is, the only possible syntax here is 'L:ea,D'. // So check ahead to see if EOL follows D, then we're good to go. - if (((*tok >= KW_A10 && *tok <= KW_BA) || (*tok >= KW_A && *tok <= KW_B)) && *(tok + 1) == EOL) + if (((*tok >= REG56_A10 && *tok <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B)) && *(tok + 1) == EOL) { //'L:ea,D' D1 = *tok++; - if (D1 == KW_A) + if (D1 == REG56_A) D1 = 4; - else if (D1 == KW_B) + else if (D1 == REG56_B) D1 = 5; else D1 &= 7; @@ -2267,10 +2267,10 @@ static inline LONG checkea(const uint32_t termchar, const int strings) if (*tok++ != '(') return error(ea_errors[strings][0]); - if (*tok >= KW_R0 && *tok <= KW_R7) + if (*tok >= REG56_R0 && *tok <= REG56_R7) { // We got '-(Rn' so mark it down - ea = DSP_EA_PREDEC1 | (*tok++ - KW_R0); + ea = DSP_EA_PREDEC1 | (*tok++ - REG56_R0); if (*tok++ != ')') return error(ea_errors[strings][1]); @@ -2286,17 +2286,17 @@ static inline LONG checkea(const uint32_t termchar, const int strings) // Checking for ea of type (Rn) tok++; - if (*tok >= KW_R0 && *tok <= KW_R7) + if (*tok >= REG56_R0 && *tok <= REG56_R7) { // We're in 'X:(Rn..)..,D', 'X:(Rn..)..,D1 Y:eay,D2', 'X:(Rn..)..,D1 S2,Y:eay' - ea = *tok++ - KW_R0; + ea = *tok++ - REG56_R0; if (*tok == '+') { // '(Rn+Nn)' tok++; - if (*tok < KW_N0 || *tok > KW_N7) + if (*tok < REG56_N0 || *tok > REG56_N7) return error(ea_errors[strings][3]); if ((*tok++ & 7) != ea) @@ -2326,7 +2326,7 @@ static inline LONG checkea(const uint32_t termchar, const int strings) ea |= DSP_EA_POSTINC1; return ea; } - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)+Nn if ((*tok++ & 7) != ea) @@ -2340,7 +2340,7 @@ static inline LONG checkea(const uint32_t termchar, const int strings) } else { - if (*tok >= KW_N0 && *tok <= KW_N7) + if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)+Nn if ((*tok++ & 7) != ea) @@ -2369,7 +2369,7 @@ static inline LONG checkea(const uint32_t termchar, const int strings) ea |= DSP_EA_POSTDEC1; return ea; } - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)-Nn if ((*tok++ & 7) != ea) @@ -2383,7 +2383,7 @@ static inline LONG checkea(const uint32_t termchar, const int strings) } else { - if (*tok >= KW_N0 && *tok <= KW_N7) + if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)-Nn if ((*tok++ & 7) != ea) @@ -2536,7 +2536,7 @@ LONG parmoves(WORD dest) if (*tok++ != ',') return error("expected comma"); - if (!((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))) + if (!((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))) return error("expected x0,x1,y0,y1,a0,b0,a2,b2,a1,b1,a,b,r0-r7,n0-n7 after immediate"); immreg = SDreg(*tok++); @@ -2724,8 +2724,8 @@ deposit_immediate_short_with_register: switch (*tok++) { - case KW_A: S2 = 0 << 9; break; - case KW_B: S2 = 1 << 9; break; + case REG56_A: S2 = 0 << 9; break; + case REG56_B: S2 = 1 << 9; break; default: return error("unrecognised X:R parallel move syntax: S2 can only be A or B in '#xxxxxx,D1 S2,D2'"); break; } @@ -2734,8 +2734,8 @@ deposit_immediate_short_with_register: switch (*tok++) { - case KW_Y0: D2 = 0 << 8; break; - case KW_Y1: D2 = 1 << 8; break; + case REG56_Y0: D2 = 0 << 8; break; + case REG56_Y1: D2 = 1 << 8; break; default: return error("unrecognised X:R parallel move syntax: D2 can only be Y0 or Y1 in '#xxxxxx,D1 S2,D2'"); break; } @@ -2747,7 +2747,7 @@ deposit_immediate_short_with_register: return inst; } } - else if (*tok == KW_X) + else if (*tok == REG56_X) { if (tok[1] == ',') // Hey look, it's just the register X and not the addressing mode - fall through to general case @@ -2761,7 +2761,7 @@ deposit_immediate_short_with_register: // 'X:ea,D' or 'X:aa,D' or 'X:ea,D1 S2,D2' or 'X:eax,D1 Y:eay,D2' or 'X:eax,D1 S2,Y:eay' return parse_x(1, 0b0100000000000000, 0, 1); } - else if (*tok == KW_Y) + else if (*tok == REG56_Y) { if (tok[1] == ',') // Hey look, it's just the register y and not the addressing mode - fall through to general case @@ -2775,7 +2775,7 @@ deposit_immediate_short_with_register: // 'Y:ea,D' or 'Y:aa,D' return parse_y(0b0100100010000000, 0, 0, 0); } - else if (*tok == KW_L) + else if (*tok == REG56_L) { // 'L:ea,D' or 'L:aa,D' tok++; @@ -2784,7 +2784,7 @@ deposit_immediate_short_with_register: return parse_l(1, 0b0100000011000000, 0); } - else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2) || (*tok >= KW_A10 && *tok <= KW_BA)) + else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2) || (*tok >= REG56_A10 && *tok <= REG56_BA)) { // Everything else - brace for impact! // R: 'S,D' @@ -2801,7 +2801,7 @@ parse_everything_else: if (*tok++ != ',') return error("Comma expected after 'S')"); - if (*tok == KW_X) + if (*tok == REG56_X) { // 'S,X:ea' 'S,X:aa' 'S,X:ea S2,D2' 'S1,X:eax Y:eay,D2' 'S1,X:eax S2,Y:eay' // 'A,X:ea X0,A' 'B,X:ea X0,B' @@ -2812,7 +2812,7 @@ parse_everything_else: return parse_x(0, 0b0100000000000000, S1, 1); } - else if (*tok == KW_Y) + else if (*tok == REG56_Y) { // 'S,Y:ea' 'S,Y:aa' tok++; @@ -2822,7 +2822,7 @@ parse_everything_else: return parse_y(0b000000000000000, S1, 0, 0); } - else if (*tok == KW_L) + else if (*tok == REG56_L) { // 'S,L:ea' 'S,L:aa' tok++; @@ -2832,7 +2832,7 @@ parse_everything_else: return parse_l(1, 0b0000000000000000, L_S1); } - else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) + else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) { // 'S,D' // 'S1,D1 Y:ea,D2' 'S1,D1 S2,Y:ea' 'S1,D1 #xxxxxx,D2' @@ -2846,7 +2846,7 @@ parse_everything_else: inst |= (S1 << 5) | (D1); return inst; } - else if (*tok == KW_Y) + else if (*tok == REG56_Y) { // 'S1,D1 Y:ea,D2' tok++; @@ -2855,7 +2855,7 @@ parse_everything_else: return parse_y(0b0001000001000000, S1, D1, 0); } - else if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1) + else if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1) { // 'Y0,A A,Y:ea' 'Y0,B B,Y:ea' 'S1,D1 S2,Y:ea' S2 = SDreg(*tok++); @@ -2866,7 +2866,7 @@ parse_everything_else: if (*tok++ != ',') return error("unrecognised Y: parallel move syntax: expected ',' after Y0,A A"); - if (*tok++ != KW_Y) + if (*tok++ != REG56_Y) return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,A A,"); if (*tok++ != ':') @@ -2888,7 +2888,7 @@ parse_everything_else: if (*tok++ != ',') return error("unrecognised Y: parallel move syntax: expected ',' after Y0,B B"); - if (*tok++ != KW_Y) + if (*tok++ != REG56_Y) return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,B B,"); if (*tok++ != ':') @@ -2910,7 +2910,7 @@ parse_everything_else: if (*tok++ != ',') return error("unrecognised Y: parallel move syntax: expected ',' after S1,D1 S2"); - if (*tok++ != KW_Y) + if (*tok++ != REG56_Y) return error("unrecognised Y: parallel move syntax: expected 'Y' after S1,D1 S2,"); if (*tok++ != ':') @@ -2959,10 +2959,10 @@ parse_everything_else: // S1 is a or b, D1 is x0 or x1 and d2 is y0, y1, a or b switch (*tok++) { - case KW_Y0: D2 = 0 << 8; break; - case KW_Y1: D2 = 1 << 8; break; - case KW_A: D2 = 2 << 8; break; - case KW_B: D2 = 3 << 8; break; + case REG56_Y0: D2 = 0 << 8; break; + case REG56_Y1: D2 = 1 << 8; break; + case REG56_A: D2 = 2 << 8; break; + case REG56_B: D2 = 3 << 8; break; default: return error("unrecognised R:Y: parallel move syntax: D2 must be y0, y1, a or b in 'S1,D1 #xxxxxx,D2'"); } @@ -2995,9 +2995,9 @@ parse_everything_else: // U 'ea' can only be '(Rn)-Nn', '(Rn)+Nn', '(Rn)-' or '(Rn)+' tok++; - if (*tok >= KW_R0 && *tok <= KW_R7) + if (*tok >= REG56_R0 && *tok <= REG56_R7) { - ea1 = (*tok++ - KW_R0); + ea1 = (*tok++ - REG56_R0); } else return error("unrecognised U parallel move syntax: expected 'Rn' after '('"); @@ -3012,7 +3012,7 @@ parse_everything_else: if (*tok == EOL) // (Rn)+ ea1 |= 3 << 3; - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)+Nn if ((*tok++ & 7) != ea1) @@ -3036,7 +3036,7 @@ parse_everything_else: ea1 |= 2 << 3; tok++; } - else if (*tok >= KW_N0 && *tok <= KW_N7) + else if (*tok >= REG56_N0 && *tok <= REG56_N7) { // (Rn)-Nn if ((*tok++ & 7) != ea1) diff --git a/dsp56k_mach.c b/dsp56k_mach.c index 0fe0316..c56bdb6 100644 --- a/dsp56k_mach.c +++ b/dsp56k_mach.c @@ -14,8 +14,8 @@ #include "sect.h" #include "token.h" -#define DEF_KW -#include "kwtab.h" +#define DEF_REG56 +#include "56kregs.h" // Globals @@ -151,12 +151,12 @@ int dsp_acc48(LONG inst) switch (dsp_a0reg) { - case KW_X: inst |= 2 << 4; break; - case KW_Y: inst |= 3 << 4; break; - case KW_X0: inst |= 4 << 4;break; - case KW_Y0: inst |= 5 << 4;break; - case KW_X1: inst |= 6 << 4;break; - case KW_Y1: inst |= 7 << 4;break; + case REG56_X: inst |= 2 << 4; break; + case REG56_Y: inst |= 3 << 4; break; + case REG56_X0: inst |= 4 << 4;break; + case REG56_Y0: inst |= 5 << 4;break; + case REG56_X1: inst |= 6 << 4;break; + case REG56_Y1: inst |= 7 << 4;break; default: return error("dsp_acc48: shouldn't reach here!"); } @@ -210,9 +210,9 @@ int dsp_immcr(LONG inst) { switch (dsp_a1reg) { - case KW_CCR: inst |= 1; break; - case KW_MR:inst |= 0; break; - case KW_OMR:inst |= 2; break; + case REG56_CCR: inst |= 1; break; + case REG56_MR:inst |= 0; break; + case REG56_OMR:inst |= 2; break; default: return error("invalid destination register (only ccr, mr, omr allowed"); } @@ -243,13 +243,13 @@ int dsp_immmovec(LONG inst) case 5: case 6: case 7: inst |= dsp_a1reg; break; // M0-M7 - case KW_SR: inst |= 25; break; - case KW_OMR: inst |= 26; break; - case KW_SP: inst |= 27; break; - case KW_SSH: inst |= 28; break; - case KW_SSL: inst |= 29; break; - case KW_LA: inst |= 30; break; - case KW_LC: inst |= 31; break; + case REG56_SR: inst |= 25; break; + case REG56_OMR: inst |= 26; break; + case REG56_SP: inst |= 27; break; + case REG56_SSH: inst |= 28; break; + case REG56_SSL: inst |= 29; break; + case REG56_LA: inst |= 30; break; + case REG56_LC: inst |= 31; break; default: return error("invalid destination register (only m0-m7, SR, OMR, SP, SSH, SSL, LA, LC allowed"); } @@ -451,7 +451,7 @@ static inline LONG tab_A18(int *am, int *reg) case M_ACC56: case M_ACC24: case M_ACC8: - if (*reg == KW_A1) + if (*reg == REG56_A1) return 4; else return (*reg & 7); @@ -460,13 +460,13 @@ static inline LONG tab_A18(int *am, int *reg) case M_DSPPCU: switch (*reg) { - case KW_SR: return 1; break; - case KW_OMR: return 2; break; - case KW_SP: return 3; break; - case KW_SSH: return 4; break; - case KW_SSL: return 5; break; - case KW_LA: return 6; break; - case KW_LC: return 7; break; + case REG56_SR: return 1; break; + case REG56_OMR: return 2; break; + case REG56_SP: return 3; break; + case REG56_SSH: return 4; break; + case REG56_SSL: return 5; break; + case REG56_LA: return 6; break; + case REG56_LC: return 7; break; default: return error("specified control register not allowed as destination"); break; @@ -926,7 +926,7 @@ int dsp_movec_ea(LONG inst) } // Abort if unsupported registers are requested - if (reg == KW_PC || reg == KW_MR || reg == KW_CCR) + if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR) return error("illegal registers for instruction."); if (dsp_am0 & C_DSPIM) @@ -997,7 +997,7 @@ int dsp_movec_aa(LONG inst) } // Abort if unsupported registers are requested - if (reg == KW_PC || reg == KW_MR || reg == KW_CCR) + if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR) return error("PC, MR, CCR are illegal registers for this instruction."); if (memspace == -1) @@ -1030,8 +1030,8 @@ int dsp_movec_reg(LONG inst) int am1 = dsp_am1; // Abort if unsupported registers are requested - if (dsp_a0reg == KW_PC || dsp_a0reg == KW_MR || dsp_a0reg == KW_CCR || - dsp_a1reg == KW_PC || dsp_a1reg == KW_MR || dsp_a1reg == KW_CCR) + if (dsp_a0reg == REG56_PC || dsp_a0reg == REG56_MR || dsp_a0reg == REG56_CCR || + dsp_a1reg == REG56_PC || dsp_a1reg == REG56_MR || dsp_a1reg == REG56_CCR) return error("PC, MR, CCR are illegal registers for this instruction."); int reg1 = tab_A18(&dsp_am0, &dsp_a0reg); @@ -1106,7 +1106,7 @@ int dsp_mult(LONG inst) return error("x0/y0/x1/y1 combination not allowed for multiplication."); } - if (dsp_a2reg == KW_B) + if (dsp_a2reg == REG56_B) inst |= 1 << 3; inst |= dsp_k; @@ -1142,7 +1142,7 @@ int dsp_movem_ea(LONG inst) } // Abort if unsupported registers are requested - if (reg == KW_PC || reg == KW_MR || reg == KW_CCR) + if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR) return error("illegal registers for instruction."); if (memspace != -1) @@ -1206,7 +1206,7 @@ int dsp_movem_aa(LONG inst) } // Abort if unsupported registers are requested - if (reg == KW_PC || reg == KW_MR || reg == KW_CCR) + if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR) return error("PC, MR, CCR are illegal registers for this instruction."); if (memspace != -1) @@ -1428,7 +1428,7 @@ int dsp_movep_reg(LONG inst) } // Abort if unsupported registers are requested - if (reg == KW_PC || reg == KW_MR || reg == KW_CCR) + if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR) return error("illegal registers for instruction."); reg2 = tab_A18(&am, ®2); diff --git a/kw.tab b/kw.tab index eb1e8bc..6e87cf6 100644 --- a/kw.tab +++ b/kw.tab @@ -1,74 +1,3 @@ -d0 128 -d1 129 -d2 130 -d3 131 -d4 132 -d5 133 -d6 134 -d7 135 - -a0 136 -a1 137 -a2 138 -a3 139 -a4 140 -a5 141 -a6 142 -a7 143 - -sp 143 -usp 184 -ssp 144 -pc 145 -sr 146 -ccr 147 - -ic40 185 -dc40 186 -bc40 187 - -sfc 188 -dfc 189 -vbr 191 - -cacr 192 -caar 193 -msp 194 -isp 195 - -tc 196 -itt0 197 -itt1 198 -dtt0 199 -dtt1 200 -mmusr 201 -psr 201 -urp 202 -srp 203 - -iacr0 204 -iacr1 205 -dacr0 206 -dacr1 207 - -tt0 208 -tt1 209 - -crp 210 - -fpiar 220 -fpsr 221 -fpcr 222 - -fp0 224 -fp1 225 -fp2 226 -fp3 227 -fp4 228 -fp5 229 -fp6 230 -fp7 231 - .equ 61 equ 61 .reg 82 @@ -82,90 +11,3 @@ equrundef 50 .regundef 50 regundef 50 set 149 - -r0 151 -r1 152 -r2 153 -r3 154 -r4 155 -r5 156 -r6 157 -r7 158 -r8 159 -r9 160 -r10 161 -r11 162 -r12 163 -r13 164 -r14 165 -r15 166 -r16 167 -r17 168 -r18 169 -r19 170 -r20 171 -r21 172 -r22 173 -r23 174 -r24 175 -r25 176 -r26 177 -r27 178 -r28 179 -r29 180 -r30 181 -r31 182 -.ccdef 183 -ccdef 183 -defined 112 -referenced 113 -streq 118 -macdef 119 -time 120 -date 121 -abscount 122 -filesize 70 - -x0 260 -x1 261 -y0 262 -y1 263 -b0 265 -b2 267 -b1 269 -a 270 -b 271 -n0 280 -n1 281 -n2 282 -n3 283 -n4 284 -n5 285 -n6 286 -n7 287 -m0 288 -m1 289 -m2 290 -m3 291 -m4 292 -m5 293 -m6 294 -m7 295 - -mr 304 -omr 305 -la 306 -lc 307 -ssh 308 -ssl 309 -ss 310 - -l 302 -p 303 - -a10 312 -b10 313 -x 314 -y 315 -ab 318 -ba 319 diff --git a/mach.c b/mach.c index 3c7a30c..1fb1607 100644 --- a/mach.c +++ b/mach.c @@ -17,8 +17,8 @@ #include "sect.h" #include "token.h" -#define DEF_KW -#include "kwtab.h" +#define DEF_REG68 +#include "68kregs.h" // Exported variables int movep = 0; // Global flag to indicate we're generating a movep instruction @@ -1073,7 +1073,7 @@ int m_movem(WORD inst, WORD siz) goto immed1; } - if ((*tok >= KW_D0) && (*tok <= KW_A7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_A7)) { // , ea if (reglist(&rmask) < 0) @@ -1365,7 +1365,7 @@ int m_cas(WORD inst, WORD siz) } // Dc - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS accepts only data registers"); inst2 = (*tok++) & 7; @@ -1374,7 +1374,7 @@ int m_cas(WORD inst, WORD siz) return error("missing comma"); // Du - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS accepts only data registers"); inst2 |= ((*tok++) & 7) << 6; @@ -1435,7 +1435,7 @@ int m_cas2(WORD inst, WORD siz) } // Dc1 - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); inst2 = (*tok++) & 7; @@ -1444,7 +1444,7 @@ int m_cas2(WORD inst, WORD siz) return error("missing colon"); // Dc2 - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); inst3 = (*tok++) & 7; @@ -1453,7 +1453,7 @@ int m_cas2(WORD inst, WORD siz) return error("missing comma"); // Du1 - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); inst2 |= ((*tok++) & 7) << 6; @@ -1462,7 +1462,7 @@ int m_cas2(WORD inst, WORD siz) return error("missing colon"); // Du2 - if ((*tok < KW_D0) && (*tok > KW_D7)) + if ((*tok < REG68_D0) && (*tok > REG68_D7)) return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); inst3 |= ((*tok++) & 7) << 6; @@ -1473,9 +1473,9 @@ int m_cas2(WORD inst, WORD siz) // Rn1 if (*tok++ != '(') return error("missing ("); - if ((*tok >= KW_D0) && (*tok <= KW_D7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) inst2 |= (((*tok++) & 7) << 12) | (0 << 15); - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + else if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) inst2 |= (((*tok++) & 7) << 12) | (1 << 15); else return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); @@ -1489,9 +1489,9 @@ int m_cas2(WORD inst, WORD siz) // Rn2 if (*tok++ != '(') return error("missing ("); - if ((*tok >= KW_D0) && (*tok <= KW_D7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) inst3 |= (((*tok++) & 7) << 12) | (0 << 15); - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + else if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) inst3 |= (((*tok++) & 7) << 12) | (1 << 15); else return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); @@ -1884,7 +1884,7 @@ int m_pack(WORD inst, WORD siz) if (siz != SIZN) return error("bad size suffix"); - if (*tok >= KW_D0 && *tok <= KW_D7) + if (*tok >= REG68_D0 && *tok <= REG68_D7) { // Dx,Dy,# inst |= (0 << 3); // R/M @@ -1893,7 +1893,7 @@ int m_pack(WORD inst, WORD siz) if (*tok != ',' && tok[2] != ',') return error("missing comma"); - if (tok[1] < KW_D0 && tok[1] > KW_D7) + if (tok[1] < REG68_D0 && tok[1] > REG68_D7) return error(syntax_error); inst |= ((tok[1] & 7)<<9); @@ -1910,10 +1910,10 @@ int m_pack(WORD inst, WORD siz) if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ',')) return error(syntax_error); - if (tok[1] < KW_A0 && tok[1] > KW_A7) + if (tok[1] < REG68_A0 && tok[1] > REG68_A7) return error(syntax_error); - if (tok[5] < KW_A0 && tok[6] > KW_A7) + if (tok[5] < REG68_A0 && tok[6] > REG68_A7) return error(syntax_error); inst |= ((tok[1] & 7) << 0); @@ -2044,13 +2044,13 @@ int m_cinv(WORD inst, WORD siz) inst |= (0 << 6) | (a1reg); switch (a0reg) { - case 0: // KW_IC40 + case 0: // REG68_IC40 inst |= (2 << 6) | (a1reg); break; - case 1: // KW_DC40 + case 1: // REG68_DC40 inst |= (1 << 6) | (a1reg); break; - case 2: // KW_BC40 + case 2: // REG68_BC40 inst |= (3 << 6) | (a1reg); break; } @@ -2247,21 +2247,21 @@ int m_pflush(WORD inst, WORD siz) fc = (uint16_t)a0exval; break; - case KW_D0: - case KW_D1: - case KW_D2: - case KW_D3: - case KW_D4: - case KW_D5: - case KW_D6: - case KW_D7: + case REG68_D0: + case REG68_D1: + case REG68_D2: + case REG68_D3: + case REG68_D4: + case REG68_D5: + case REG68_D6: + case REG68_D7: fc = (1 << 4) | (*tok++ & 7); break; - case KW_SFC: + case REG68_SFC: fc = 0; tok++; break; - case KW_DFC: + case REG68_DFC: fc = 1; tok++; break; @@ -2333,7 +2333,7 @@ int m_pflush(WORD inst, WORD siz) if (*tok != '(' && tok[2] != ')') return error(syntax_error); - if (tok[1] < KW_A0 && tok[1] > KW_A7) + if (tok[1] < REG68_A0 && tok[1] > REG68_A7) return error("expected (An)"); if ((inst & 7) == 7) @@ -2438,9 +2438,9 @@ int m_pload(WORD inst, WORD siz, WORD extension) switch (am0) { case CREG: - if (a0reg == KW_SFC - KW_SFC) + if (a0reg == REG68_SFC - REG68_SFC) inst = 0; - else if (a0reg == KW_DFC - KW_SFC) + else if (a0reg == REG68_DFC - REG68_SFC) inst = 1; else return error("illegal control register specified"); @@ -2514,15 +2514,15 @@ int m_pmove(WORD inst, WORD siz) // and the transparent translation registers(TT0 and TT1). // It is a word operation for the MMU status register. - if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC))) + if (((reg == (REG68_URP - REG68_SFC)) || (reg == (REG68_SRP - REG68_SFC))) && ((siz != SIZD) && (siz != SIZN))) return error(siz_error); - if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC))) + if (((reg == (REG68_TC - REG68_SFC)) || (reg == (REG68_TT0 - REG68_SFC)) || (reg == (REG68_TT1 - REG68_SFC))) && ((siz != SIZL) && (siz != SIZN))) return error(siz_error); - if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN))) + if ((reg == (REG68_MMUSR - REG68_SFC)) && ((siz != SIZW) && (siz != SIZN))) return error(siz_error); if (am0 == CREG) @@ -2536,19 +2536,19 @@ int m_pmove(WORD inst, WORD siz) D_word(inst); } - switch (reg + KW_SFC) + switch (reg + REG68_SFC) { - case KW_TC: + case REG68_TC: inst2 |= (0 << 10) + (1 << 14); break; - case KW_SRP: + case REG68_SRP: inst2 |= (2 << 10) + (1 << 14); break; - case KW_CRP: + case REG68_CRP: inst2 |= (3 << 10) + (1 << 14); break; - case KW_TT0: + case REG68_TT0: inst2 |= (2 << 10) + (0 << 13); break; - case KW_TT1: + case REG68_TT1: inst2 |= (3 << 10) + (0 << 13); break; - case KW_MMUSR: + case REG68_MMUSR: if (am0 == CREG) inst2 |= (1 << 9) + (3 << 13); else @@ -2637,9 +2637,9 @@ int m_ptest(WORD inst, WORD siz, WORD extension) switch (am0) { case CREG: - if (a0reg == KW_SFC - KW_SFC) + if (a0reg == REG68_SFC - REG68_SFC) extension |= 0; - else if (a0reg == KW_DFC - KW_SFC) + else if (a0reg == REG68_DFC - REG68_SFC) extension |= 1; else return error("illegal control register specified"); @@ -2684,7 +2684,7 @@ int m_ptest(WORD inst, WORD siz, WORD extension) { CHECK_COMMA - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { extension |= (1 << 8) | ((*tok++ & 7) << 4); } @@ -3338,7 +3338,7 @@ int m_fmovem(WORD inst, WORD siz) if (siz == SIZX || siz == SIZN) { - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) { // fmovem.x ,ea if (fpu_reglist_left(®mask) < 0) @@ -3361,7 +3361,7 @@ int m_fmovem(WORD inst, WORD siz) ea0gen(siz); return OK; } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { // fmovem.x Dn,ea datareg = (*tok++ & 7) << 10; @@ -3399,7 +3399,7 @@ int m_fmovem(WORD inst, WORD siz) if (*tok++ != ',') return error("missing comma"); - if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) { // fmovem.x ea, if (fpu_reglist_right(®mask) < 0) @@ -3431,14 +3431,14 @@ int m_fmovem(WORD inst, WORD siz) } else if (siz == SIZL) { - if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR)) + if ((*tok == REG68_FPCR) || (*tok == REG68_FPSR) || (*tok == REG68_FPIAR)) { // fmovem.l ,ea regmask = (1 << 15) | (1 << 13); int no_control_regs = 0; fmovem_loop_1: - if (*tok == KW_FPCR) + if (*tok == REG68_FPCR) { regmask |= (1 << 12); tok++; @@ -3446,7 +3446,7 @@ fmovem_loop_1: goto fmovem_loop_1; } - if (*tok == KW_FPSR) + if (*tok == REG68_FPSR) { regmask |= (1 << 11); tok++; @@ -3454,7 +3454,7 @@ fmovem_loop_1: goto fmovem_loop_1; } - if (*tok == KW_FPIAR) + if (*tok == REG68_FPIAR) { regmask |= (1 << 10); tok++; @@ -3501,21 +3501,21 @@ fmovem_loop_1: regmask = (1 << 15) | (0 << 13); fmovem_loop_2: - if (*tok == KW_FPCR) + if (*tok == REG68_FPCR) { regmask |= (1 << 12); tok++; goto fmovem_loop_2; } - if (*tok == KW_FPSR) + if (*tok == REG68_FPSR) { regmask |= (1 << 11); tok++; goto fmovem_loop_2; } - if (*tok == KW_FPIAR) + if (*tok == REG68_FPIAR) { regmask |= (1 << 10); tok++; diff --git a/makefile b/makefile index f630ce2..9f6d9ac 100644 --- a/makefile +++ b/makefile @@ -66,6 +66,21 @@ risckw.h: risc.tab kwgen opkw.h: op.tab kwgen ./kwgen mo opkw.h +68kregs.h: 68kregs.tab kwgen + ./kwgen reg68 <68kregs.tab >68kregs.h + +56kregs.h: 56kregs.tab kwgen + ./kwgen reg56 <56kregs.tab >56kregs.h + +6502regs.h: 6502regs.tab kwgen + ./kwgen reg65 <6502regs.tab >6502regs.h + +riscregs.h: riscregs.tab kwgen + ./kwgen regrisc riscregs.h + +unarytab.h: unary.tab kwgen + ./kwgen unary unarytab.h + # Looks like this is not needed... dsp56kkw.h: dsp56k.tab kwgen ./kwgen dsp dsp56kkw.h @@ -93,21 +108,21 @@ rmac: $(OBJS) # clean: - $(RM) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen 68k.tab kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h dsp56kgen dsp56kgen.o dsp56k.tab dsp56kkw.h dsp56ktab.h + $(RM) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen 68k.tab kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h dsp56kgen dsp56kgen.o dsp56k.tab dsp56kkw.h dsp56ktab.h 68kregs.h 56kregs.h 6502regs.h riscregs.h unarytab.h # # Dependencies # 6502.o: 6502.c direct.h rmac.h symbol.h token.h expr.h error.h mach.h \ - procln.h riscasm.h sect.h kwtab.h + procln.h riscasm.h sect.h kwtab.h 6502regs.h 68kgen: 68kgen.c amode.o: amode.c amode.h rmac.h symbol.h error.h expr.h mach.h procln.h \ - token.h sect.h riscasm.h kwtab.h mntab.h parmode.h + token.h sect.h riscasm.h kwtab.h mntab.h parmode.h 68kregs.h debug.o: debug.c debug.h rmac.h symbol.h amode.h direct.h token.h expr.h \ mark.h sect.h riscasm.h direct.o: direct.c direct.h rmac.h symbol.h token.h 6502.h amode.h \ error.h expr.h fltpoint.h listing.h mach.h macro.h mark.h procln.h \ - riscasm.h sect.h kwtab.h + riscasm.h sect.h kwtab.h 56kregs.h riscregs.h dsp56k.o: dsp56k.c rmac.h symbol.h dsp56k.h sect.h riscasm.h dsp56k_amode.o: dsp56k_amode.c dsp56k_amode.h rmac.h symbol.h amode.h \ error.h token.h expr.h procln.h sect.h riscasm.h kwtab.h mntab.h @@ -142,9 +157,8 @@ rmac.o: rmac.c rmac.h symbol.h 6502.h debug.h direct.h token.h error.h \ expr.h listing.h mark.h macro.h object.h procln.h riscasm.h sect.h \ version.h sect.o: sect.c sect.h rmac.h symbol.h riscasm.h 6502.h direct.h token.h \ - error.h expr.h listing.h mach.h mark.h + error.h expr.h listing.h mach.h mark.h riscregs.h symbol.o: symbol.c symbol.h error.h rmac.h listing.h object.h procln.h \ token.h token.o: token.c token.h rmac.h symbol.h direct.h error.h macro.h \ - procln.h sect.h riscasm.h kwtab.h - + procln.h sect.h riscasm.h kwtab.h unarytab.h diff --git a/maketabs.bat b/maketabs.bat index c5947a9..70b8ad6 100644 --- a/maketabs.bat +++ b/maketabs.bat @@ -43,6 +43,36 @@ if not exist %FILE2% GOTO BUILD for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i if %NEWEST%==%FILE1% GOTO BUILD +SET FILE1=68kregs.tab +SET FILE2=68kregs.h +if not exist %FILE2% GOTO BUILD +for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i +if %NEWEST%==%FILE1% GOTO BUILD + +SET FILE1=56kregs.tab +SET FILE2=56kregs.h +if not exist %FILE2% GOTO BUILD +for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i +if %NEWEST%==%FILE1% GOTO BUILD + +SET FILE1=6502regs.tab +SET FILE2=6502regs.h +if not exist %FILE2% GOTO BUILD +for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i +if %NEWEST%==%FILE1% GOTO BUILD + +SET FILE1=riscregs.tab +SET FILE2=riscregs.h +if not exist %FILE2% GOTO BUILD +for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i +if %NEWEST%==%FILE1% GOTO BUILD + +SET FILE1=unary.tab +SET FILE2=unarytab.h +if not exist %FILE2% GOTO BUILD +for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i +if %NEWEST%==%FILE1% GOTO BUILD + GOTO END :BUILD @@ -58,7 +88,11 @@ kwgen dsp dsp56kkw.h kwgen mp <6502.tab >6502kw.h kwgen mp <6502.tab >6502kw.h kwgen mo opkw.h - +kwgen reg68 <68kregs.tab >68kregs.h +kwgen reg56 <56kregs.tab >56kregs.h +kwgen reg65 <6502regs.tab >6502regs.h +kwgen regrisc riscregs.h +kwgen unary unarytab.h rem touch files that include these header files so they'll recompile echo Generating tables... diff --git a/parmode.h b/parmode.h index bf835b2..c03be6e 100644 --- a/parmode.h +++ b/parmode.h @@ -17,12 +17,12 @@ // Dn // An // # expression - if ((*tok >= KW_D0) && (*tok <= KW_D7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { AMn = DREG; AnREG = *tok++ & 7; } - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + else if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AMn = AREG; AnREG = *tok++ & 7; @@ -58,7 +58,7 @@ int ea_PC = 0; // Flag that let us know if we have PC or An relative ea tok++; - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AnREG = *tok++ & 7; @@ -80,7 +80,7 @@ AMn = AINDEXED; goto AMn_IX0; // Handle ",Xn[.siz][*scale])" } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { // Since index register isn't used here, store register number in this field AnIXREG = *tok++ & 7; // (Dn) @@ -206,7 +206,7 @@ else return error("unhandled so far"); } - else if (*tok == KW_PC) + else if (*tok == REG68_PC) { // (PC,Xn[.siz][*scale]) tok++; AMn = PCINDEXED; @@ -224,7 +224,7 @@ AMn_IXN: // Handle any indexed (tok -> a comma) if (*tok++ != ',') goto badmode; - if (*tok < KW_D0 || *tok > KW_A7) + if (*tok < REG68_D0 || *tok > REG68_A7) goto badmode; AnIXREG = *tok++ & 15; @@ -370,19 +370,19 @@ AMn_IXN: // Handle any indexed (tok -> a comma) // Check for address register or PC, suppress base register // otherwise - if (*tok == KW_PC) + if (*tok == REG68_PC) { // ([bd,PC,... ea_PC = 3; // Set flag in order to set proper value to AMn below when we can make a decision on ea // (why "3"? Well, MEMPOST is 3 away from PCMPOST, etc. Have a look at amode.h) AnREG = (7 << 3) | 3; // PC is special case - stuff 011 to register field and 111 to the mode field tok++; } - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + else if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { // ([bd,An,... AnREG = (6 << 3) | (*tok & 7); tok++; } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { // ([bd,Dn,... AnREG = (6 << 3); @@ -498,13 +498,13 @@ AMn_IXN: // Handle any indexed (tok -> a comma) else tok++; // eat the comma - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AnIXREG = ((*tok & 7) << 12); AnEXTEN |= EXT_A; tok++; } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { AnEXTEN |= ((*tok & 7) << 12); AnEXTEN |= EXT_D; @@ -741,13 +741,13 @@ IS_SUPPRESSEDn: tok++; // ([bd,An,Xn.size*scale],od) // Check for Xn - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AnEXTEN |= ((*tok & 7) << 12); AnEXTEN |= EXT_A; tok++; } - else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + else if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { AnEXTEN |= ((*tok & 7) << 12); AnEXTEN |= EXT_D; @@ -934,7 +934,7 @@ IS_SUPPRESSEDn: if (*tok++ != ',') goto badmode; - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AnREG = *tok & 7; tok++; @@ -965,7 +965,7 @@ IS_SUPPRESSEDn: AnBEXVAL = AnEXVAL; AnBEXATTR = AnEXATTR; - if ((*tok >= KW_D0) && (*tok <= KW_D7)) + if ((*tok >= REG68_D0) && (*tok <= REG68_D7)) { AnEXTEN |= ((*tok++) & 7) << 12; // Check for size @@ -1062,7 +1062,7 @@ IS_SUPPRESSEDn: else goto badmode; } - else if (*tok == KW_PC) + else if (*tok == REG68_PC) { if (*++tok == ',') { // expr(PC,Xn...) @@ -1082,56 +1082,56 @@ IS_SUPPRESSEDn: goto badmode; } } - else if (*tok == '-' && tok[1] == '(' && ((tok[2] >= KW_A0) && (tok[2] <= KW_A7)) && tok[3] == ')') + else if (*tok == '-' && tok[1] == '(' && ((tok[2] >= REG68_A0) && (tok[2] <= REG68_A7)) && tok[3] == ')') { AMn = APREDEC; AnREG = tok[2] & 7; tok += 4; } - else if (*tok == KW_CCR) + else if (*tok == REG68_CCR) { AMn = AM_CCR; tok++; goto AnOK; } - else if (*tok == KW_SR) + else if (*tok == REG68_SR) { AMn = AM_SR; tok++; goto AnOK; } - else if (*tok == KW_USP) + else if (*tok == REG68_USP) { AMn = AM_USP; tok++; AnREG = 2; // Added this for the case of USP used in movec (see CREGlut in mach.c). Hopefully nothing gets broken! goto AnOK; } - else if ((*tok >= KW_IC40) && (*tok <= KW_BC40)) + else if ((*tok >= REG68_IC40) && (*tok <= REG68_BC40)) { AMn = CACHES; - AnREG = *tok++ - KW_IC40; + AnREG = *tok++ - REG68_IC40; // After a cache keyword only a comma or EOL is allowed if ((*tok != ',') && (*tok != EOL)) return ERROR; goto AnOK; } - else if ((*tok >= KW_SFC) && (*tok <= KW_CRP)) + else if ((*tok >= REG68_SFC) && (*tok <= REG68_CRP)) { AMn = CREG; - AnREG = (*tok++) - KW_SFC; + AnREG = (*tok++) - REG68_SFC; goto AnOK; } - else if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + else if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7)) { AMn = FREG; AnREG = (*tok++ & 7); } - else if ((*tok >= KW_FPIAR) && (*tok <= KW_FPCR)) + else if ((*tok >= REG68_FPIAR) && (*tok <= REG68_FPCR)) { AMn = FPSCR; - AnREG = (1 << ((*tok++) - KW_FPIAR + 10)); + AnREG = (1 << ((*tok++) - REG68_FPIAR + 10)); } // expr // expr.w @@ -1192,7 +1192,7 @@ CHK_FOR_DISPn: tok++; - if ((*tok >= KW_A0) && (*tok <= KW_A7)) + if ((*tok >= REG68_A0) && (*tok <= REG68_A7)) { AnREG = *tok++ & 7; @@ -1206,7 +1206,7 @@ CHK_FOR_DISPn: AMn = AINDEXED; goto AMn_IXN; } - else if (*tok == KW_PC) + else if (*tok == REG68_PC) { if (*++tok == ')') { diff --git a/procln.c b/procln.c index ef7bf1c..4af12bd 100644 --- a/procln.c +++ b/procln.c @@ -28,6 +28,8 @@ #define DEF_MN // Incl 68k keyword definitions #define DECL_MN // Incl 68k keyword state machine tables #include "mntab.h" +#define DEF_REG68 // Incl 68k register definitions +#include "68kregs.h" #define DEF_MR #define DECL_MR @@ -44,7 +46,8 @@ #define DEF_DSP // Include DSP56K keywords definitions #define DECL_DSP // Include DSP56K keyword state machine tables #include "dsp56kkw.h" - +#define DEF_REG56 // Include DSP56K register definitions +#include "56kregs.h" IFENT * ifent; // Current ifent static IFENT ifent0; // Root ifent @@ -200,10 +203,7 @@ loop1: // Internal line processing loop // First token MUST be a symbol (Shamus: not sure why :-/) if (*tok != SYMBOL) { - if ((*tok >= KW_D0) && (*tok <= KW_R31)) - error("cannot use reserved keyword as label name or .equ"); - else - error("syntax error; expected symbol"); + error("syntax error; expected symbol"); goto loop; } @@ -437,7 +437,7 @@ When checking to see if it's already been equated, issue a warning. // Check for register to equate to // This check will change once we split the registers per architecture into their own tables // and out of kw.tab. But for now it'll do... - if ((*tok >= KW_D0) && (*tok <= KW_BA)) + if ((*tok >= REG68_D0) && (*tok <= REG56_BA)) { sy->sattre = EQUATEDREG; // Mark as equated register equreg = *tok; diff --git a/riscasm.c b/riscasm.c index 706cac8..e31c104 100644 --- a/riscasm.c +++ b/riscasm.c @@ -20,8 +20,8 @@ #define DEF_MR // Declare keyword values #include "risckw.h" // Incl. generated risc keywords -#define DEF_KW // Declare keyword values -#include "kwtab.h" // Incl. generated keyword tables & defs +#define DEF_REGRISC +#include "riscregs.h" // Incl. generated keyword tables & defs #define MAXINTERNCC 26 // Maximum internal condition codes @@ -165,7 +165,7 @@ static inline int MalformedOpcode(int signal) // static inline int IllegalIndexedRegister(int reg) { - return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0); + return error("Attempted index reference with non-indexable register (r%d)", reg - REGRISC_R0); } // @@ -202,9 +202,9 @@ static int EvaluateRegisterFromTokenStream(uint32_t fixup) // Firstly, check to see if it's a register token and return that. No // need to invoke expr() for easy cases like this. int reg = *tok & 255; - if (reg >= KW_R0 && reg <= KW_R31) + if (reg >= REGRISC_R0 && reg <= REGRISC_R31) { - reg -= KW_R0; + reg -= REGRISC_R0; tok++; return reg; } @@ -233,6 +233,7 @@ static int EvaluateRegisterFromTokenStream(uint32_t fixup) // We shouldn't get here, that should not be legal interror(9); + return 0; // Not that this will ever execute, but let's be nice and pacify gcc warnings } // @@ -421,7 +422,7 @@ int GenerateRISCCode(int state) // PC,Rd or Rs,Rd case RI_MOVE: - if (*tok == KW_PC) + if (*tok == REGRISC_PC) { parm = 51; reg1 = 0; @@ -451,8 +452,8 @@ int GenerateRISCCode(int state) if ((tok[1] == '+') || (tok[1] == '-')) { // Trying to make indexed call - if ((*tok == KW_R14) || (*tok == KW_R15)) - indexed = (*tok - KW_R0); + if ((*tok == REGRISC_R14) || (*tok == REGRISC_R15)) + indexed = (*tok - REGRISC_R0); else return IllegalIndexedRegister(*tok); } @@ -472,7 +473,7 @@ int GenerateRISCCode(int state) parm = (WORD)(reg1 - 14 + 58); tok++; - if ((*tok >= KW_R0) && (*tok <= KW_R31)) + if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31)) indexed = 1; if (*tok == SYMBOL) @@ -548,8 +549,8 @@ int GenerateRISCCode(int state) tok++; indexed = 0; - if (((*tok == KW_R14) || (*tok == KW_R15)) && (tok[1] != ')')) - indexed = *tok - KW_R0; + if (((*tok == REGRISC_R14) || (*tok == REGRISC_R15)) && (tok[1] != ')')) + indexed = *tok - REGRISC_R0; if (!indexed) { @@ -566,7 +567,7 @@ int GenerateRISCCode(int state) parm = (WORD)(reg2 - 14 + 60); tok++; - if ((*tok >= KW_R0) && (*tok <= KW_R31)) + if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31)) indexed = 1; if (*tok == SYMBOL) diff --git a/riscregs.tab b/riscregs.tab new file mode 100644 index 0000000..4716a85 --- /dev/null +++ b/riscregs.tab @@ -0,0 +1,35 @@ +pc 145 + +r0 151 +r1 152 +r2 153 +r3 154 +r4 155 +r5 156 +r6 157 +r7 158 +r8 159 +r9 160 +r10 161 +r11 162 +r12 163 +r13 164 +r14 165 +r15 166 +r16 167 +r17 168 +r18 169 +r19 170 +r20 171 +r21 172 +r22 173 +r23 174 +r24 175 +r25 176 +r26 177 +r27 178 +r28 179 +r29 180 +r30 181 +r31 182 + diff --git a/rmac.c b/rmac.c index 1f3bcb1..145a965 100644 --- a/rmac.c +++ b/rmac.c @@ -45,6 +45,10 @@ int dsp56001; // Assembling DSP 56001 code int list_fd; // File to write listing to int segpadsize; // Segment padding size int endian; // Host processor endianess (0 = LE, 1 = BE) +int *regbase; // Points to current DFA register table (base) +int *regtab; // Points to current DFA register table (tab) +int *regcheck; // Points to current DFA register table (check) +int *regaccept; // Points to current DFA register table (accept) char * objfname; // Object filename pointer char * firstfname; // First source filename char * cmdlnexec; // Executable name, pointer to ARGV[0] @@ -284,6 +288,11 @@ int ParseOptimization(char * optstring) return OK; } +extern int reg68base[53]; +extern int reg68tab[222]; +extern int reg68check[222]; +extern int reg68accept[222]; + // // Process command line arguments and do an assembly // @@ -321,6 +330,10 @@ int Process(int argc, char ** argv) dsp_orgmap[0].start = 0; // Initialize 56001 org initial address dsp_orgmap[0].memtype = ORG_P; // Initialize 56001 org start segment m6502 = 0; // 6502 mode off by default + regbase = reg68base; // Initialise DFA register tables + regtab = reg68tab; // Idem + regcheck = reg68check; // Idem + regaccept = reg68accept; // Idem // Initialize modules InitSymbolTable(); // Symbol table diff --git a/rmac.h b/rmac.h index d03d010..44ed972 100644 --- a/rmac.h +++ b/rmac.h @@ -311,6 +311,10 @@ extern int activecpu; extern int activefpu; extern uint32_t org68k_address; extern int org68k_active; +extern int *regbase; +extern int *regtab; +extern int *regcheck; +extern int *regaccept; // Exported functions void strtoupper(char * s); diff --git a/sect.c b/sect.c index 3cedbb2..b20542b 100644 --- a/sect.c +++ b/sect.c @@ -18,9 +18,8 @@ #include "riscasm.h" #include "symbol.h" #include "token.h" -#define DEF_KW -#include "kwtab.h" -#undef DEF_KW +#define DEF_REGRISC +#include "riscregs.h" // Function prototypes void MakeSection(int, uint16_t); @@ -722,7 +721,7 @@ int ResolveFixups(int sno) } else if ((dw & FUMASKRISC) == FU_REGONE) { - eval -= KW_R0; + eval -= REGRISC_R0; if (eval > 31) { error("register one value out of range"); @@ -736,7 +735,7 @@ int ResolveFixups(int sno) } else if ((dw & FUMASKRISC) == FU_REGTWO) { - eval -= KW_R0; + eval -= REGRISC_R0; if (eval > 31) { error("register two value out of range"); diff --git a/token.c b/token.c index 10b2832..ce2df41 100644 --- a/token.c +++ b/token.c @@ -19,6 +19,13 @@ #define DECL_KW // Declare keyword arrays #define DEF_KW // Declare keyword values #include "kwtab.h" // Incl generated keyword tables & defs +#define DEF_REG68 // Incl 68k register definitions +#include "68kregs.h" +#define DEF_REGRISC // Include GPU/DSP register definitions +#include "riscregs.h" +#define DEF_UNARY // Declare unary values +#define DECL_UNARY // Incl uanry keyword state machine tables +#include "unarytab.h" // Incl generated unary tables & defs int lnsave; // 1; strcpy() text of current line @@ -147,6 +154,7 @@ static char * regname[] = { "a10","b10","x","y","","","ab","ba" // 312,319 }; +WARNING("We should get rid of this table, it's a subset of the table above") static char * riscregname[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", @@ -509,14 +517,14 @@ arg_num: // This is a hack. It might be better table-driven. d = NULL; - if ((*tk >= KW_D0) && !rdsp && !rgpu) + if ((*tk >= REG68_D0) && !rdsp && !rgpu) { - d = regname[(int)*tk++ - KW_D0]; + d = regname[(int)*tk++ - REG68_D0]; goto strcopy; } - else if ((*tk >= KW_R0) && (*tk <= KW_R31)) + else if ((*tk >= REGRISC_R0) && (*tk <= REGRISC_R31)) { - d = riscregname[(int)*tk++ - KW_R0]; + d = riscregname[(int)*tk++ - REGRISC_R0]; goto strcopy; } else @@ -1156,14 +1164,15 @@ DEBUG { printf("TokenizeLine: Calling fpop() from SRC_IFILE...\n"); } // If the symbol is small, check to see if it's really the name of // a register. - if (j <= KWSIZE) + uint8_t *p2 = p; + if (j <= 5) { - for(state=0; state>=0;) + for (state = 0; state >= 0;) { j = (int)tolowertab[*p++]; - j += kwbase[state]; + j += regbase[state]; - if (kwcheck[j] != state) + if (regcheck[j] != state) { j = -1; break; @@ -1171,38 +1180,48 @@ DEBUG { printf("TokenizeLine: Calling fpop() from SRC_IFILE...\n"); } if (*p == EOS || p == ln) { - j = kwaccept[j]; + j = regaccept[j]; + goto skip_keyword; break; } - state = kwtab[j]; + state = regtab[j]; } } - else - { - j = -1; - } - // Make j = -1 if user tries to use a RISC register while in 68K mode - if (!(rgpu || rdsp || dsp56001) && ((TOKEN)j >= KW_R0 && (TOKEN)j <= KW_R31)) + // Scan for keywords + if ((j <= 0 || state <= 0) || p==p2) { - j = -1; + if (j <= KWSIZE) + { + for (state = 0; state >= 0;) + { + j = (int)tolowertab[*p2++]; + j += kwbase[state]; + + if (kwcheck[j] != state) + { + j = -1; + break; + } + + if (*p == EOS || p2 == ln) + { + j = kwaccept[j]; + break; + } + + state = kwtab[j]; + } + } + else + { + j = -1; + } } - // Make j = -1 if time, date etc with no preceeding ^^ - // defined, referenced, streq, macdef, date and time - switch ((TOKEN)j) - { - case 112: // defined - case 113: // referenced - case 118: // streq - case 119: // macdef - case 120: // time - case 121: // date - case KW_FILESIZE: // filesize - j = -1; - } - + skip_keyword: + // If we detected equrundef/regundef set relevant flag if (j == KW_EQURUNDEF) { @@ -1530,14 +1549,14 @@ dostring: for(state=0; state>=0;) { // Get char, convert to lowercase - j = *p++; + j = (int)tolowertab[*p++]; - if (j >= 'A' && j <= 'Z') - j += 0x20; + //if (j >= 'A' && j <= 'Z') + // j += 0x20; - j += kwbase[state]; + j += unarybase[state]; - if (kwcheck[j] != state) + if (unarycheck[j] != state) { j = -1; break; @@ -1545,11 +1564,11 @@ dostring: if (*p == EOS || p == ln) { - j = kwaccept[j]; + j = unaryaccept[j]; break; } - state = kwtab[j]; + state = unarytab[j]; } if (j < 0 || state < 0) diff --git a/unary.tab b/unary.tab new file mode 100644 index 0000000..105c7f6 --- /dev/null +++ b/unary.tab @@ -0,0 +1,11 @@ +.ccdef 183 +ccdef 183 +defined 112 +referenced 113 + +streq 118 +macdef 119 +time 120 +date 121 +filesize 70 +abscount 122 -- 2.33.0.windows.1 From ff5ce4d73aa761bc1b764b2a08ea73ce8ab663ae Mon Sep 17 00:00:00 2001 From: ggn Date: Thu, 24 Mar 2022 13:29:40 +0200 Subject: [PATCH 3/4] Printing a listing with -l* now doesn't print \f characters when printing the symbol table. --- listing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/listing.c b/listing.c index 3130887..d5a2296 100644 --- a/listing.c +++ b/listing.c @@ -53,7 +53,7 @@ static char * month[16] = { // int eject(void) { - if (listing > 0) + if (listing > 0 && list_pag) { println("\f"); nlines = 0; -- 2.33.0.windows.1 From d599c66677726d7ae8fcc8efa727cb743ac8a68b Mon Sep 17 00:00:00 2001 From: ggn Date: Thu, 24 Mar 2022 13:43:45 +0200 Subject: [PATCH 4/4] Removed redundant table --- token.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/token.c b/token.c index ce2df41..ed0785c 100644 --- a/token.c +++ b/token.c @@ -154,14 +154,6 @@ static char * regname[] = { "a10","b10","x","y","","","ab","ba" // 312,319 }; -WARNING("We should get rid of this table, it's a subset of the table above") -static char * riscregname[] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" -}; - // // Initialize tokenizer @@ -517,16 +509,11 @@ arg_num: // This is a hack. It might be better table-driven. d = NULL; - if ((*tk >= REG68_D0) && !rdsp && !rgpu) + if (*tk >= REG68_D0) { d = regname[(int)*tk++ - REG68_D0]; goto strcopy; } - else if ((*tk >= REGRISC_R0) && (*tk <= REGRISC_R31)) - { - d = riscregname[(int)*tk++ - REGRISC_R0]; - goto strcopy; - } else { switch ((int)*tk++) -- 2.33.0.windows.1